c4x.c (c4x_fp_reglist): Const-ify.

	* c4x.c (c4x_fp_reglist): Const-ify.
	* cris.c (cris_print_operand): Likewise.
	* i386.c (ix86_va_arg): Likewise.
	* ia64/unwind-ia64.c (unw_decode_table): Likewise.
	* m32r.c (m32r_hard_regno_mode_ok): Likewise.
	* m32r.h (m32r_hard_regno_mode_ok): Likewise.
	* mcore.c (regno_reg_class, mcore_unique_section): Likewise.
	* mcore.h (regno_reg_class): Likewise.
	* mips.c (gen_int_relational): Likewise.
	* ns32k.c (ns32k_reg_class_contents, regclass_map): Likewise.
	* ns32k.h (ns32k_reg_class_contents, regclass_map): Likewise.
	* pdp11.c (pdp11_assemble_integer): Likewise.
	* pj.h (INITIALIZE_TRAMPOLINE): Likewise.
	* s390.c (s390_branch_condition_mnemonic, regclass_map):
	Likewise.
	* s390.h (regclass_map): Likewise.
	* sh.c (shift_amounts): Likewise.
	* sh.md (rot_tab): Likewise.

From-SVN: r50517

18 files changed, 43 insertions, 22 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 56d2cf6..27eb895 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,24 @@
+2002-03-09  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* c4x.c (c4x_fp_reglist): Const-ify.
+	* cris.c (cris_print_operand): Likewise.
+	* i386.c (ix86_va_arg): Likewise.
+	* ia64/unwind-ia64.c (unw_decode_table): Likewise.
+	* m32r.c (m32r_hard_regno_mode_ok): Likewise.
+	* m32r.h (m32r_hard_regno_mode_ok): Likewise.
+	* mcore.c (regno_reg_class, mcore_unique_section): Likewise.
+	* mcore.h (regno_reg_class): Likewise.
+	* mips.c (gen_int_relational): Likewise.
+	* ns32k.c (ns32k_reg_class_contents, regclass_map): Likewise.
+	* ns32k.h (ns32k_reg_class_contents, regclass_map): Likewise.
+	* pdp11.c (pdp11_assemble_integer): Likewise.
+	* pj.h (INITIALIZE_TRAMPOLINE): Likewise.
+	* s390.c (s390_branch_condition_mnemonic, regclass_map):
+	Likewise.
+	* s390.h (regclass_map): Likewise.
+	* sh.c (shift_amounts): Likewise.
+	* sh.md (rot_tab): Likewise.
+
 2002-03-09  Geoffrey Keating  <geoffk@redhat.com>
 
 	* config/rs6000/rs6000.md (ne0+4): Add extra CLOBBER.
diff --git a/gcc/config/c4x/c4x.c b/gcc/config/c4x/c4x.c
index e34ed5c..fc02849 100644
--- a/gcc/config/c4x/c4x.c
+++ b/gcc/config/c4x/c4x.c
@@ -514,7 +514,7 @@ static const int c4x_int_reglist[3][6] =
   {AR2_REGNO, RC_REGNO, RS_REGNO, RE_REGNO, 0, 0}
 };
 
-static int c4x_fp_reglist[2] = {R2_REGNO, R3_REGNO};
+static const int c4x_fp_reglist[2] = {R2_REGNO, R3_REGNO};
 
 
 /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a
diff --git a/gcc/config/cris/cris.c b/gcc/config/cris/cris.c
index 72fc6b3..9456874 100644
--- a/gcc/config/cris/cris.c
+++ b/gcc/config/cris/cris.c
@@ -1264,7 +1264,7 @@ cris_print_operand (file, x, code)
   rtx operand = x;
 
   /* Size-strings corresponding to MULT expressions.  */
-  static const char *mults[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" };
+  static const char *const mults[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" };
 
   /* New code entries should just be added to the switch below.  If
      handling is finished, just return.  If handling was just a
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 2f7bb73..ae714da6 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -2509,7 +2509,7 @@ rtx
 ix86_va_arg (valist, type)
      tree valist, type;
 {
-  static int intreg[6] = { 0, 1, 2, 3, 4, 5 };
+  static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
   tree f_gpr, f_fpr, f_ovf, f_sav;
   tree gpr, fpr, ovf, sav, t;
   int size, rsize;
diff --git a/gcc/config/ia64/unwind-ia64.c b/gcc/config/ia64/unwind-ia64.c
index 99923aa..bca3f23 100644
--- a/gcc/config/ia64/unwind-ia64.c
+++ b/gcc/config/ia64/unwind-ia64.c
@@ -1212,7 +1212,7 @@ unw_decode_b3_x4 (unsigned char *dp, unsigned char code, void *arg)
 
 typedef unsigned char *(*unw_decoder) (unsigned char *, unsigned char, void *);
 
-static unw_decoder unw_decode_table[2][8] =
+static const unw_decoder unw_decode_table[2][8] =
 {
   /* prologue table: */
   {
diff --git a/gcc/config/m32r/m32r.c b/gcc/config/m32r/m32r.c
index 0a98559..acc6b5e 100644
--- a/gcc/config/m32r/m32r.c
+++ b/gcc/config/m32r/m32r.c
@@ -172,7 +172,7 @@ enum m32r_mode_class
 
 /* Value is 1 if register/mode pair is acceptable on arc.  */
 
-unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
+const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
 {
   T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
   T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
diff --git a/gcc/config/m32r/m32r.h b/gcc/config/m32r/m32r.h
index 02a9168..ef51ce1 100644
--- a/gcc/config/m32r/m32r.h
+++ b/gcc/config/m32r/m32r.h
@@ -638,7 +638,7 @@ extern enum m32r_sdata m32r_sdata;
 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 
 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.  */
-extern unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER];
+extern const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER];
 extern unsigned int m32r_mode_class[];
 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
 ((m32r_hard_regno_mode_ok[REGNO] & m32r_mode_class[MODE]) != 0)
diff --git a/gcc/config/mcore/mcore.c b/gcc/config/mcore/mcore.c
index 931cd06..2acd158 100644
--- a/gcc/config/mcore/mcore.c
+++ b/gcc/config/mcore/mcore.c
@@ -62,7 +62,7 @@ rtx arch_compare_op1;
 
 /* Provides the class number of the smallest class containing
    reg number.  */
-int regno_reg_class[FIRST_PSEUDO_REGISTER] =
+const int regno_reg_class[FIRST_PSEUDO_REGISTER] =
 {
   GENERAL_REGS,	ONLYR1_REGS,  LRW_REGS,	    LRW_REGS,
   LRW_REGS,	LRW_REGS,     LRW_REGS,	    LRW_REGS,
@@ -3519,7 +3519,7 @@ mcore_unique_section (decl, reloc)
      int reloc ATTRIBUTE_UNUSED;
 {
   int len;
-  char * name;
+  const char * name;
   char * string;
   const char * prefix;
 
diff --git a/gcc/config/mcore/mcore.h b/gcc/config/mcore/mcore.h
index 0133675..1de6fbc 100644
--- a/gcc/config/mcore/mcore.h
+++ b/gcc/config/mcore/mcore.h
@@ -518,7 +518,7 @@ enum reg_class
    reg number REGNO.  This could be a conditional expression
    or could index an array.  */
 
-extern int regno_reg_class[FIRST_PSEUDO_REGISTER];
+extern const int regno_reg_class[FIRST_PSEUDO_REGISTER];
 #define REGNO_REG_CLASS(REGNO) regno_reg_class[REGNO]
 
 /* When defined, the compiler allows registers explicitly used in the
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 72a1e9c..467cbca 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -2884,7 +2884,7 @@ gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
     int unsignedp;		/* != 0 for unsigned comparisons.  */
   };
 
-  static struct cmp_info info[ (int)ITEST_MAX ] = {
+  static const struct cmp_info info[ (int)ITEST_MAX ] = {
 
     { XOR,	 0,  65535,  0,	 0,  0,	 0, 0 },	/* EQ  */
     { XOR,	 0,  65535,  0,	 0,  1,	 1, 0 },	/* NE  */
@@ -2900,7 +2900,7 @@ gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
 
   enum internal_test test;
   enum machine_mode mode;
-  struct cmp_info *p_info;
+  const struct cmp_info *p_info;
   int branch_p;
   int eqne_p;
   int invert;
diff --git a/gcc/config/ns32k/ns32k.c b/gcc/config/ns32k/ns32k.c
index 7c3afe2..9feef5e 100644
--- a/gcc/config/ns32k/ns32k.c
+++ b/gcc/config/ns32k/ns32k.c
@@ -47,9 +47,9 @@ int ns32k_num_files = 0;
    initialized in time. Also this is more convenient as an array of ints.
    We know that HARD_REG_SET fits in an unsigned int */
 
-unsigned int ns32k_reg_class_contents[N_REG_CLASSES][1] = REG_CLASS_CONTENTS;
+const unsigned int ns32k_reg_class_contents[N_REG_CLASSES][1] = REG_CLASS_CONTENTS;
 
-enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
+const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
 {
   GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
   GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
diff --git a/gcc/config/ns32k/ns32k.h b/gcc/config/ns32k/ns32k.h
index 58878a2..00d3aa7 100644
--- a/gcc/config/ns32k/ns32k.h
+++ b/gcc/config/ns32k/ns32k.h
@@ -1388,8 +1388,8 @@ do {									\
 
 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address(FILE, ADDR)
 
-extern unsigned int ns32k_reg_class_contents[N_REG_CLASSES][1];
-extern enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; /* smallest class containing REGNO */
+extern const unsigned int ns32k_reg_class_contents[N_REG_CLASSES][1];
+extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; /* smallest class containing REGNO */
 
 /*
 Local variables:
diff --git a/gcc/config/pdp11/pdp11.c b/gcc/config/pdp11/pdp11.c
index 5054565..cff6fbf 100644
--- a/gcc/config/pdp11/pdp11.c
+++ b/gcc/config/pdp11/pdp11.c
@@ -984,7 +984,7 @@ pdp11_assemble_integer (x, size, aligned_p)
 
 /* register move costs, indexed by regs */
 
-static int move_costs[N_REG_CLASSES][N_REG_CLASSES] = 
+static const int move_costs[N_REG_CLASSES][N_REG_CLASSES] = 
 {
              /* NO  MUL  GEN  LFPU  NLFPU FPU ALL */
 
diff --git a/gcc/config/pj/pj.h b/gcc/config/pj/pj.h
index 42065f5..5c0095e 100644
--- a/gcc/config/pj/pj.h
+++ b/gcc/config/pj/pj.h
@@ -734,7 +734,7 @@ struct pj_args
 
 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)                             \
 {                                                                             \
-  static int off[4] = { 1, 0, 4, 3 };                                         \
+  static const int off[4] = { 1, 0, 4, 3 };                                   \
   int i;                                                                      \
                                                                               \
   /* Move the FNADDR and CXT into the instruction stream. Do this byte        \
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index 38c6f59..f4696e4 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -344,7 +344,7 @@ s390_branch_condition_mnemonic (code, inv)
      rtx code;
      int inv;
 {
-  static const char *mnemonic[16] =
+  static const char *const mnemonic[16] =
     {
       NULL, "o", "h", "nle",
       "l", "nhe", "lh", "ne",
@@ -600,7 +600,7 @@ override_options ()
 
 /* Map for smallest class containing reg regno.  */
 
-enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
+const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
   ADDR_REGS,    ADDR_REGS, ADDR_REGS, ADDR_REGS,
   ADDR_REGS,    ADDR_REGS, ADDR_REGS, ADDR_REGS,
diff --git a/gcc/config/s390/s390.h b/gcc/config/s390/s390.h
index 959bc9c..005c2f3 100644
--- a/gcc/config/s390/s390.h
+++ b/gcc/config/s390/s390.h
@@ -518,7 +518,7 @@ enum reg_class
 
 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
 
-extern enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; /* smalled class containing REGNO   */
+extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; /* smalled class containing REGNO   */
 
 /* The class value for index registers, and the one for base regs.  */
 
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index 10f342c..882a778 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -1136,7 +1136,7 @@ static const char shift_insns[]    =
    One bit right shifts clobber the T bit, so when possible, put one bit
    shifts in the middle of the sequence, so the ends are eligible for
    branch delay slots.  */
-static short shift_amounts[32][5] = {
+static const short shift_amounts[32][5] = {
   {0}, {1}, {2}, {2, 1},
   {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
   {8}, {8, 1}, {8, 2}, {8, 1, 2},
diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index 072a33e..ad17f11 100644
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -2013,7 +2013,7 @@
   "TARGET_SH1"
   "
 {
-  static char rot_tab[] = {
+  static const char rot_tab[] = {
     000, 000, 000, 000, 000, 000, 010, 001,
     001, 001, 011, 013, 003, 003, 003, 003,
     003, 003, 003, 003, 003, 013, 012, 002,