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author | Uros Bizjak <uros@gcc.gnu.org> | 2019-06-17 20:40:22 +0200 |
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committer | Uros Bizjak <uros@gcc.gnu.org> | 2019-06-17 20:40:22 +0200 |
commit | a064fd4c7385442dd4f9f3a1b538aef2fdac5209 (patch) | |
tree | 8f24018f01d949be7aed5c71b94ea8254f667a31 /gcc | |
parent | bf0af866a4f2792a91310d8b809e25ffbdd9e1f7 (diff) | |
download | gcc-a064fd4c7385442dd4f9f3a1b538aef2fdac5209.zip gcc-a064fd4c7385442dd4f9f3a1b538aef2fdac5209.tar.gz gcc-a064fd4c7385442dd4f9f3a1b538aef2fdac5209.tar.bz2 |
re PR target/62055 (missed optimization: recognize fnabs (FP negative absolute value) (x86-64))
PR target/62055
* config/i386/i386.md (*nabstf2_1): New insn pattern.
(*nabs<mode>2_1): Ditto.
(nabs sse-reg splitter): New splitter.
* config/i386/sse.md (*nabs<mode>2): New insn_and_split pattern.
testsuite/ChangeLog:
PR target/62055
* gcc.target/i386/fnabs.c: New test.
From-SVN: r272396
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/ChangeLog | 8 | ||||
-rw-r--r-- | gcc/config/i386/i386.md | 52 | ||||
-rw-r--r-- | gcc/config/i386/sse.md | 27 | ||||
-rw-r--r-- | gcc/testsuite/ChangeLog | 7 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/i386/fnabs.c | 21 |
5 files changed, 114 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c114a5dc..6001d26 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2019-06-17 Uroš Bizjak <ubizjak@gmail.com> + + PR target/62055 + * config/i386/i386.md (*nabstf2_1): New insn pattern. + (*nabs<mode>2_1): Ditto. + (nabs sse-reg splitter): New splitter. + * config/i386/sse.md (*nabs<mode>2): New insn_and_split pattern. + 2019-06-17 Jan Hubicka <hubicka@ucw.cz> PR bootstrap/90873. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 8406aed..2b7df20 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -9452,6 +9452,16 @@ "#" [(set_attr "isa" "noavx,noavx,avx,avx")]) +(define_insn "*nabstf2_1" + [(set (match_operand:TF 0 "register_operand" "=x,x,Yv,Yv") + (neg:TF + (abs:TF + (match_operand:TF 1 "vector_operand" "0,xBm,Yv,m")))) + (use (match_operand:TF 2 "vector_operand" "xBm,0,Yvm,Yv"))] + "TARGET_SSE" + "#" + [(set_attr "isa" "noavx,noavx,avx,avx")]) + (define_expand "<code><mode>2" [(set (match_operand:X87MODEF 0 "register_operand") (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand")))] @@ -9553,6 +9563,48 @@ [(const_int 0)] "ix86_split_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;") +(define_insn "*nabs<mode>2_1" + [(set (match_operand:MODEF 0 "register_operand" "=x,x,Yv") + (neg:MODEF + (abs:MODEF + (match_operand:MODEF 1 "register_operand" "0,x,Yv")))) + (use (match_operand:<ssevecmode> 2 "vector_operand" "xBm,0,Yvm"))] + "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH" + "#" + [(set_attr "isa" "noavx,noavx,avx")]) + +(define_split + [(set (match_operand:SSEMODEF 0 "sse_reg_operand") + (neg:SSEMODEF + (abs:SSEMODEF + (match_operand:SSEMODEF 1 "vector_operand")))) + (use (match_operand:<ssevecmodef> 2 "vector_operand"))] + "((SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH) + || (TARGET_SSE && (<MODE>mode == TFmode))) + && reload_completed" + [(set (match_dup 0) (match_dup 3))] +{ + machine_mode mode = <MODE>mode; + machine_mode vmode = <ssevecmodef>mode; + + operands[0] = lowpart_subreg (vmode, operands[0], mode); + operands[1] = lowpart_subreg (vmode, operands[1], mode); + + if (TARGET_AVX) + { + if (MEM_P (operands[1])) + std::swap (operands[1], operands[2]); + } + else + { + if (operands_match_p (operands[0], operands[2])) + std::swap (operands[1], operands[2]); + } + + operands[3] + = gen_rtx_fmt_ee (IOR, vmode, operands[1], operands[2]); +}) + ;; Conditionalize these after reload. If they match before reload, we ;; lose the clobber and ability to use integer instructions. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index d7d5425..5d8ada4 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1748,6 +1748,33 @@ } [(set_attr "isa" "noavx,noavx,avx,avx")]) +(define_insn_and_split "*nabs<mode>2" + [(set (match_operand:VF 0 "register_operand" "=x,x,v,v") + (neg:VF + (abs:VF + (match_operand:VF 1 "vector_operand" "0,xBm,v,m")))) + (use (match_operand:VF 2 "vector_operand" "xBm,0,vm,v"))] + "TARGET_SSE" + "#" + "&& reload_completed" + [(set (match_dup 0) (match_dup 3))] +{ + if (TARGET_AVX) + { + if (MEM_P (operands[1])) + std::swap (operands[1], operands[2]); + } + else + { + if (operands_match_p (operands[0], operands[2])) + std::swap (operands[1], operands[2]); + } + + operands[3] + = gen_rtx_fmt_ee (IOR, <MODE>mode, operands[1], operands[2]); +} + [(set_attr "isa" "noavx,noavx,avx,avx")]) + (define_expand "<plusminus_insn><mode>3<mask_name><round_name>" [(set (match_operand:VF 0 "register_operand") (plusminus:VF diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 688c6f3..d2ea2f7 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2019-06-17 Uroš Bizjak <ubizjak@gmail.com> + + PR target/62055 + * gcc.target/i386/fnabs.c: New test. + 2019-06-17 Marek Polacek <polacek@redhat.com> PR c++/83820 - excessive attribute arguments not detected. @@ -22,7 +27,7 @@ 2019-06-16 Jozef Lawrynowicz <jozef.l@mittosystems.com> - * lib/target-supports.exp: Add check_effective_target_longlong64. + * lib/target-supports.exp: Add check_effective_target_longlong64. 2019-06-16 Jan Hubicka <hubicka@ucw.cz> diff --git a/gcc/testsuite/gcc.target/i386/fnabs.c b/gcc/testsuite/gcc.target/i386/fnabs.c new file mode 100644 index 0000000..817c9a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/fnabs.c @@ -0,0 +1,21 @@ +/* PR target/62055 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2 -mfpmath=sse" } */ + +float testf (float a) +{ + return -__builtin_fabsf (a); +} + +double test (double a) +{ + return -__builtin_fabs (a); +} + +__float128 testq (__float128 a) +{ + return -__builtin_fabsq (a); +} + +/* { dg-final { scan-assembler-times "\tv?orp\[sd\]\[ \t\]" 2 } } */ +/* { dg-final { scan-assembler-times "\tv?por\[ \t\]" 1 } } */ |