predicates.md (reg_or_arith_cint_operand): Delete.

	* config/rs6000/predicates.md (reg_or_arith_cint_operand): Delete.
	(reg_or_add_cint_operand): Rename from reg_or_add_cint64_operand.
	Handle SImode.
	(reg_or_sub_cint_operand): Likewise.
	(mask_operand): Handle DImode.
	(mask64_operand): Delete.
	(and64_operand): Delete.
	* config/rs6000/rs6000.c (num_insns_constant): Use mask_operand
	instead of mask64_operand.
	(print_operand): Likewise.
	(rs6000_rtx_costs): Use mask_operand and reg_or_add_cint_operand and
	reg_or_sub_cint_operand instead of *64_* variants.
	* config/rs6000/rs6000.h (EXTRA_CONSTRAINT): Use mask_operand
	instead of mask64_operand.
	* config/rs6000/rs6000.md: Use mask_operand and and_operand instead
	of *64_* variants.
	(FP): New.
	(add_op2): Delete.
	(add<mode>3): Use reg_or_add_cint_operand.
	(sub_op2): Delete.
	(sub<mode>3): Use reg_or_sub_cint_operand.
	(udiv<mode>3, div<mode>3, div<mode>3_no_mq, mod<mode>3,
	mov<mode>_internal2, mov<mode>, cmp<mode>, cmp<mode>,
	cmp<mode>_internal1, indirect_jump<mode>, ctr<mode>,
	ctr<mode>_internal1, ctr<mode>_internal2, ctr<mode>_internal5,
	ctr<mode>_internal6, save_fpregs_<mode>, return_internal_<mode>,
	return_and_restore_fpregs_<mode>, eh_set_lr_<mode>,
	various unnamed patterns): New.
	(udivsi3, divsi3, divsi3_no_mq, modsi3, movsi_internal2, movsi,
	cmpsi, cmpsi_internal1, indirect_jumpsi, ctrsi, ctrsi_internal1,
	ctrsi_internal2, ctrsi_internal5, ctrsi_internal6, save_fpregs_si,
	return_internal_si, return_and_restore_fpregs_si, eh_set_lr_si,
	udivdi3, divdi3, divdi3_no_mq, moddi3, movdi_internal2, movdi,
	cmpdi, cmpdi_internal1, indirect_jumpdi, ctrdi, ctrdi_internal1,
	ctrdi_internal2, ctrdi_internal5, ctrdi_internal6, save_fpregs_di,
	return_internal_di, return_and_restore_fpregs_di, eh_set_lr_di,
	movhi, movqi, cmpsf, cmpdf, cmptf, various unnamed patterns):
	Delete.

From-SVN: r100852

5 files changed, 261 insertions, 803 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9fa2255..4a6d731 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,44 @@
+2005-06-11  Geoffrey Keating  <geoffk@apple.com>
+
+	* config/rs6000/predicates.md (reg_or_arith_cint_operand): Delete.
+	(reg_or_add_cint_operand): Rename from reg_or_add_cint64_operand.
+	Handle SImode.
+	(reg_or_sub_cint_operand): Likewise.
+	(mask_operand): Handle DImode.
+	(mask64_operand): Delete.
+	(and64_operand): Delete.
+	* config/rs6000/rs6000.c (num_insns_constant): Use mask_operand
+	instead of mask64_operand.
+	(print_operand): Likewise.
+	(rs6000_rtx_costs): Use mask_operand and reg_or_add_cint_operand and
+	reg_or_sub_cint_operand instead of *64_* variants.
+	* config/rs6000/rs6000.h (EXTRA_CONSTRAINT): Use mask_operand
+	instead of mask64_operand.
+	* config/rs6000/rs6000.md: Use mask_operand and and_operand instead
+	of *64_* variants.
+	(FP): New.
+	(add_op2): Delete.
+	(add<mode>3): Use reg_or_add_cint_operand.
+	(sub_op2): Delete.
+	(sub<mode>3): Use reg_or_sub_cint_operand.
+	(udiv<mode>3, div<mode>3, div<mode>3_no_mq, mod<mode>3,
+	mov<mode>_internal2, mov<mode>, cmp<mode>, cmp<mode>,
+	cmp<mode>_internal1, indirect_jump<mode>, ctr<mode>,
+	ctr<mode>_internal1, ctr<mode>_internal2, ctr<mode>_internal5,
+	ctr<mode>_internal6, save_fpregs_<mode>, return_internal_<mode>,
+	return_and_restore_fpregs_<mode>, eh_set_lr_<mode>,
+	various unnamed patterns): New.
+	(udivsi3, divsi3, divsi3_no_mq, modsi3, movsi_internal2, movsi,
+	cmpsi, cmpsi_internal1, indirect_jumpsi, ctrsi, ctrsi_internal1,
+	ctrsi_internal2, ctrsi_internal5, ctrsi_internal6, save_fpregs_si,
+	return_internal_si, return_and_restore_fpregs_si, eh_set_lr_si,
+	udivdi3, divdi3, divdi3_no_mq, moddi3, movdi_internal2, movdi,
+	cmpdi, cmpdi_internal1, indirect_jumpdi, ctrdi, ctrdi_internal1,
+	ctrdi_internal2, ctrdi_internal5, ctrdi_internal6, save_fpregs_di,
+	return_internal_di, return_and_restore_fpregs_di, eh_set_lr_di,
+	movhi, movqi, cmpsf, cmpdf, cmptf, various unnamed patterns):
+	Delete.
+
 2005-06-11  Gabriel Dos Reis  <gdr@integrable-solutions.net>
 
 	* rtl.h (to_rtx_code): Remove.
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 936f932..cba7337 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -143,30 +143,25 @@
 					   (TARGET_32BIT ? 'L' : 'J'))")
     (match_operand 0 "gpc_reg_operand")))
 
-;; Return 1 if op is a 32-bit signed constant integer valid for arithmetic
+;; Return 1 if op is a constant integer valid for addition
 ;; or non-special register.
-(define_predicate "reg_or_arith_cint_operand"
+(define_predicate "reg_or_add_cint_operand"
   (if_then_else (match_code "const_int")
-    (match_test "HOST_BITS_PER_WIDE_INT == 32
-		 || ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000)
-		     < (unsigned HOST_WIDE_INT) 0x100000000ll)")
-    (match_operand 0 "gpc_reg_operand")))
-
-;; Return 1 if op is a 32-bit signed constant integer valid for 64-bit addition
-;; or non-special register.
-(define_predicate "reg_or_add_cint64_operand"
-  (if_then_else (match_code "const_int")
-    (match_test "(HOST_BITS_PER_WIDE_INT == 32 && INTVAL (op) < 0x7fff8000)
+    (match_test "(HOST_BITS_PER_WIDE_INT == 32
+		  && (mode == SImode || INTVAL (op) < 0x7fff8000))
 		 || ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
 		     < (unsigned HOST_WIDE_INT) 0x100000000ll)")
     (match_operand 0 "gpc_reg_operand")))
 
-;; Return 1 if op is a 32-bit constant integer valid for 64-bit subtraction
+;; Return 1 if op is a constant integer valid for subtraction
 ;; or non-special register.
-(define_predicate "reg_or_sub_cint64_operand"
+(define_predicate "reg_or_sub_cint_operand"
   (if_then_else (match_code "const_int")
-    (match_test "(HOST_BITS_PER_WIDE_INT == 32 && INTVAL (op) < 0x7fff8000)
-		 || ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000)
+    (match_test "(HOST_BITS_PER_WIDE_INT == 32
+		  && (mode == SImode || - INTVAL (op) < 0x7fff8000))
+		 || ((unsigned HOST_WIDE_INT) (- INTVAL (op) 
+					       + (mode == SImode
+						  ? 0x80000000 : 0x80008000))
 		     < (unsigned HOST_WIDE_INT) 0x100000000ll)")
     (match_operand 0 "gpc_reg_operand")))
 
@@ -439,10 +434,14 @@
        (and (not (match_operand 0 "logical_operand"))
 	    (match_operand 0 "reg_or_logical_cint_operand"))))
 
-;; Return 1 if op is a constant that can be encoded in a 32-bit mask (no
-;; more than two 1->0 or 0->1 transitions).  Reject all ones and all
-;; zeros, since these should have been optimized away and confuse the
-;; making of MB and ME.
+;; For SImode, return 1 if op is a constant that can be encoded in a
+;; 32-bit mask (no more than two 1->0 or 0->1 transitions).  Reject
+;; all ones and all zeros, since these should have been optimized away
+;; and confuse the making of MB and ME.
+;; For DImode, return 1 if the operand is a constant that is a
+;; PowerPC64 mask (no more than one 1->0 or 0->1 transitions).  Reject
+;; all zeros, since zero should have been optimized away and confuses
+;; the making of MB and ME.
 (define_predicate "mask_operand"
   (match_code "const_int")
 {
@@ -452,7 +451,11 @@
 
   /* Fail in 64-bit mode if the mask wraps around because the upper
      32-bits of the mask will all be 1s, contrary to GCC's internal view.  */
-  if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001)
+  if (mode == SImode && TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001)
+    return 0;
+
+  /* Reject all zeros or all ones in 32-bit mode.  */
+  if (c == 0 || (mode == SImode && c == -1))
     return 0;
 
   /* We don't change the number of transitions by inverting,
@@ -460,21 +463,20 @@
   if (c & 1)
     c = ~c;
 
-  /* Reject all zeros or all ones.  */
-  if (c == 0)
-    return 0;
-
   /* Find the first transition.  */
   lsb = c & -c;
 
-  /* Invert to look for a second transition.  */
-  c = ~c;
+  if (mode == SImode)
+    {
+      /* Invert to look for a second transition.  */
+      c = ~c;
 
-  /* Erase first transition.  */
-  c &= -lsb;
+      /* Erase first transition.  */
+      c &= -lsb;
 
-  /* Find the second transition (if any).  */
-  lsb = c & -c;
+      /* Find the second transition (if any).  */
+      lsb = c & -c;
+    }
 
   /* Match if all the bits above are 1's (or c is zero).  */
   return c == -lsb;
@@ -502,33 +504,7 @@
   return c == -lsb;
 })
 
-;; Return 1 if the operand is a constant that is a PowerPC64 mask (no more
-;; than one 1->0 or 0->1 transitions).  Reject all zeros, since zero
-;; should have been optimized away and confuses the making of MB and ME.
-(define_predicate "mask64_operand"
-  (match_code "const_int")
-{
-  HOST_WIDE_INT c, lsb;
-
-  c = INTVAL (op);
-
-  /* Reject all zeros.  */
-  if (c == 0)
-    return 0;
-
-  /* We don't change the number of transitions by inverting,
-     so make sure we start with the LS bit zero.  */
-  if (c & 1)
-    c = ~c;
-
-  /* Find the transition, and check that all bits above are 1's.  */
-  lsb = c & -c;
-
-  /* Match if all the bits above are 1's (or c is zero).  */
-  return c == -lsb;
-})
-
-;; Like mask64_operand, but allow up to three transitions.  This
+;; Like mask_operand, but allow up to three transitions.  This
 ;; predicate is used by insn patterns that generate two rldicl or
 ;; rldicr machine insns.
 (define_predicate "mask64_2_operand"
@@ -537,15 +513,7 @@
   return mask64_1or2_operand (op, mode, false);
 })
 
-;; Return 1 if the operand is either a non-special register or a constant
-;; that can be used as the operand of a PowerPC64 logical AND insn.
-(define_predicate "and64_operand"
-  (ior (match_operand 0 "mask64_operand")
-       (if_then_else (match_test "fixed_regs[CR0_REGNO]")
-	 (match_operand 0 "gpc_reg_operand")
-	 (match_operand 0 "logical_operand"))))
-
-;; Like and64_operand, but also match constants that can be implemented
+;; Like and_operand, but also match constants that can be implemented
 ;; with two rldicl or rldicr insns.
 (define_predicate "and64_2_operand"
   (ior (and (match_code "const_int")
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 95ed9e0..db7f851 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1948,7 +1948,7 @@ num_insns_constant (rtx op, enum machine_mode mode)
     case CONST_INT:
 #if HOST_BITS_PER_WIDE_INT == 64
       if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
-	  && mask64_operand (op, mode))
+	  && mask_operand (op, mode))
 	return 2;
       else
 #endif
@@ -1990,7 +1990,7 @@ num_insns_constant (rtx op, enum machine_mode mode)
 		|| (high == -1 && low < 0))
 	      return num_insns_constant_wide (low);
 	    
-	    else if (mask64_operand (op, mode))
+	    else if (mask_operand (op, mode))
 	      return 2;
 	    
 	    else if (low == 0)
@@ -9880,7 +9880,7 @@ print_operand (FILE *file, rtx x, int code)
       /* PowerPC64 mask position.  All 0's is excluded.
 	 CONST_INT 32-bit mask is considered sign-extended so any
 	 transition must occur within the CONST_INT, not on the boundary.  */
-      if (! mask64_operand (x, DImode))
+      if (! mask_operand (x, DImode))
 	output_operand_lossage ("invalid %%S value");
 
       uval = INT_LOWPART (x);
@@ -17594,9 +17594,9 @@ rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
 	  return true;
 	}
       else if ((outer_code == PLUS
-		&& reg_or_add_cint64_operand (x, VOIDmode))
+		&& reg_or_add_cint_operand (x, VOIDmode))
 	       || (outer_code == MINUS
-		   && reg_or_sub_cint64_operand (x, VOIDmode))
+		   && reg_or_sub_cint_operand (x, VOIDmode))
 	       || ((outer_code == SET
 		    || outer_code == IOR
 		    || outer_code == XOR)
@@ -17613,7 +17613,7 @@ rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
 	  && ((outer_code == AND
 	       && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
 		   || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
-		   || mask64_operand (x, DImode)))
+		   || mask_operand (x, DImode)))
 	      || ((outer_code == IOR || outer_code == XOR)
 		  && CONST_DOUBLE_HIGH (x) == 0
 		  && (CONST_DOUBLE_LOW (x)
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 11a52bf..1e97028 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1099,14 +1099,14 @@ enum reg_class
 #define EXTRA_CONSTRAINT(OP, C)						\
   ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG	\
    : (C) == 'R' ? legitimate_constant_pool_address_p (OP)		\
-   : (C) == 'S' ? mask64_operand (OP, DImode)				\
+   : (C) == 'S' ? mask_operand (OP, DImode)				\
    : (C) == 'T' ? mask_operand (OP, SImode)				\
    : (C) == 'U' ? (DEFAULT_ABI == ABI_V4				\
 		   && small_data_operand (OP, GET_MODE (OP)))		\
    : (C) == 't' ? (mask64_2_operand (OP, DImode)			\
 		   && (fixed_regs[CR0_REGNO]				\
 		       || !logical_operand (OP, DImode))		\
-		   && !mask64_operand (OP, DImode))			\
+		   && !mask_operand (OP, DImode))			\
    : (C) == 'W' ? (easy_vector_constant (OP, GET_MODE (OP)))		\
    : (C) == 'Y' ? (word_offset_memref_operand (OP, GET_MODE (OP)))      \
    : (C) == 'Z' ? (indexed_or_indirect_operand (OP, GET_MODE (OP)))	\
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 6b72b56..8e4fd35 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -134,6 +134,12 @@
 ; (one with a '.') will compare.
 (define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
 
+; Any hardware-supported floating-point mode
+(define_mode_macro FP [(SF "TARGET_HARD_FLOAT")
+  (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
+  (TF "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
+   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128")])
+
 ; Various instructions that come in SI and DI forms.
 (define_mode_attr larx [(SI "lwarx") (DI "ldarx")])
 (define_mode_attr stcx [(SI "stwcx.") (DI "stdcx.")])
@@ -1007,13 +1013,10 @@
 
 ;; Fixed-point arithmetic insns.
 
-(define_mode_attr add_op2 [(SI "reg_or_arith_cint_operand")
-			   (DI "reg_or_add_cint64_operand")])
-
 (define_expand "add<mode>3"
   [(set (match_operand:SDI 0 "gpc_reg_operand" "")
 	(plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
-		  (match_operand:SDI 2 "<add_op2>" "")))]
+		  (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
   ""
   "
 {
@@ -1321,13 +1324,10 @@
 		    (const_int 0)))]
   "")
 
-(define_mode_attr sub_op2 [(SI "reg_or_arith_cint_operand")
-			   (DI "reg_or_sub_cint64_operand")])
-
 (define_expand "sub<mode>3"
   [(set (match_operand:SDI 0 "gpc_reg_operand" "")
 	(minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
-		   (match_operand:SDI 2 "<sub_op2>" "")))]
+		   (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
   ""
   "
 {
@@ -1945,10 +1945,10 @@
   "divs %0,%1,%2"
   [(set_attr "type" "idiv")])
 
-(define_expand "udivsi3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-        (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
-                 (match_operand:SI 2 "gpc_reg_operand" "")))]
+(define_expand "udiv<mode>3"
+  [(set (match_operand:GPR 0 "gpc_reg_operand" "")
+        (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
+		  (match_operand:GPR 2 "gpc_reg_operand" "")))]
   "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
   "
 {
@@ -1977,21 +1977,21 @@
   [(set_attr "type" "idiv")])
 
 (define_insn "*udivsi3_no_mq"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-        (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-                 (match_operand:SI 2 "gpc_reg_operand" "r")))]
+  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+        (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
+		  (match_operand:GPR 2 "gpc_reg_operand" "r")))]
   "TARGET_POWERPC && ! TARGET_POWER"
-  "divwu %0,%1,%2"
+  "div<wd>u %0,%1,%2"
   [(set_attr "type" "idiv")])
 
 ;; For powers of two we can do srai/aze for divide and then adjust for
 ;; modulus.  If it isn't a power of two, FAIL on POWER so divmodsi4 will be
 ;; used; for PowerPC, force operands into register and do a normal divide;
 ;; for AIX common-mode, use quoss call on register operands.
-(define_expand "divsi3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(div:SI (match_operand:SI 1 "gpc_reg_operand" "")
-		(match_operand:SI 2 "reg_or_cint_operand" "")))]
+(define_expand "div<mode>3"
+  [(set (match_operand:GPR 0 "gpc_reg_operand" "")
+	(div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
+		 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
   ""
   "
 {
@@ -2029,18 +2029,18 @@
   "divw %0,%1,%2"
   [(set_attr "type" "idiv")])
 
-(define_insn "*divsi3_no_mq"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-        (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-                (match_operand:SI 2 "gpc_reg_operand" "r")))]
+(define_insn "*div<mode>3_no_mq"
+  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+        (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
+		 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
   "TARGET_POWERPC && ! TARGET_POWER"
-  "divw %0,%1,%2"
+  "div<wd> %0,%1,%2"
   [(set_attr "type" "idiv")])
 
-(define_expand "modsi3"
-  [(use (match_operand:SI 0 "gpc_reg_operand" ""))
-   (use (match_operand:SI 1 "gpc_reg_operand" ""))
-   (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
+(define_expand "mod<mode>3"
+  [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
+   (use (match_operand:GPR 1 "gpc_reg_operand" ""))
+   (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
   ""
   "
 {
@@ -2053,46 +2053,47 @@
       || (i = exact_log2 (INTVAL (operands[2]))) < 0)
     FAIL;
 
-  temp1 = gen_reg_rtx (SImode);
-  temp2 = gen_reg_rtx (SImode);
+  temp1 = gen_reg_rtx (<MODE>mode);
+  temp2 = gen_reg_rtx (<MODE>mode);
 
-  emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
-  emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
-  emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
+  emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
+  emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
+  emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
   DONE;
 }")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
-		(match_operand:SI 2 "exact_log2_cint_operand" "N")))]
+  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+	(div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
+		 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
   ""
-  "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
+  "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
   [(set_attr "type" "two")
    (set_attr "length" "8")])
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			    (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
+	(compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
+			   (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
 		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r"))]
+   (clobber (match_scratch:P 3 "=r,r"))]
   ""
   "@
-   {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
+   {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
    #"
   [(set_attr "type" "compare")
    (set_attr "length" "8,12")])
 
 (define_split
   [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			    (match_operand:SI 2 "exact_log2_cint_operand" ""))
+	(compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
+			     (match_operand:GPR 2 "exact_log2_cint_operand"
+			      ""))
 		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))]
+   (clobber (match_scratch:GPR 3 ""))]
   "reload_completed"
   [(set (match_dup 3)
-	(div:SI (match_dup 1) (match_dup 2)))
+	(div:<MODE> (match_dup 1) (match_dup 2)))
    (set (match_dup 0)
 	(compare:CC (match_dup 3)
 		    (const_int 0)))]
@@ -2100,28 +2101,29 @@
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-			    (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
+	(compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
+			   (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(div:SI (match_dup 1) (match_dup 2)))]
+   (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
+	(div:P (match_dup 1) (match_dup 2)))]
   ""
   "@
-   {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
+   {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
    #"
   [(set_attr "type" "compare")
    (set_attr "length" "8,12")])
 
 (define_split
   [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			    (match_operand:SI 2 "exact_log2_cint_operand" ""))
+	(compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
+			     (match_operand:GPR 2 "exact_log2_cint_operand"
+			      ""))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(div:SI (match_dup 1) (match_dup 2)))]
+   (set (match_operand:GPR 0 "gpc_reg_operand" "")
+	(div:GPR (match_dup 1) (match_dup 2)))]
   "reload_completed"
   [(set (match_dup 0)
-	(div:SI (match_dup 1) (match_dup 2)))
+	(div:<MODE> (match_dup 1) (match_dup 2)))
    (set (match_dup 3)
 	(compare:CC (match_dup 0)
 		    (const_int 0)))]
@@ -2362,15 +2364,15 @@
 
 (define_split
   [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			    (match_operand:SI 2 "and_operand" ""))
+	(compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
+			     (match_operand:GPR 2 "and_operand" ""))
 		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))
+   (clobber (match_scratch:GPR 3 ""))
    (clobber (match_scratch:CC 4 ""))]
   "reload_completed"
   [(parallel [(set (match_dup 3)
-		   (and:SI (match_dup 1)
-			   (match_dup 2)))
+		   (and:<MODE> (match_dup 1)
+			       (match_dup 2)))
 	      (clobber (match_dup 4))])
    (set (match_dup 0)
 	(compare:CC (match_dup 3)
@@ -6033,127 +6035,6 @@
   "mulhdu %0,%1,%2"
   [(set_attr "type" "lmul")])
 
-(define_expand "divdi3"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(div:DI (match_operand:DI 1 "gpc_reg_operand" "")
-		(match_operand:DI 2 "reg_or_cint_operand" "")))]
-  "TARGET_POWERPC64"
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && INTVAL (operands[2]) > 0
-      && exact_log2 (INTVAL (operands[2])) >= 0)
-    ;
-  else
-    operands[2] = force_reg (DImode, operands[2]);
-}")
-
-(define_expand "moddi3"
-  [(use (match_operand:DI 0 "gpc_reg_operand" ""))
-   (use (match_operand:DI 1 "gpc_reg_operand" ""))
-   (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
-  "TARGET_POWERPC64"
-  "
-{
-  int i;
-  rtx temp1;
-  rtx temp2;
-
-  if (GET_CODE (operands[2]) != CONST_INT
-      || INTVAL (operands[2]) <= 0
-      || (i = exact_log2 (INTVAL (operands[2]))) < 0)
-    FAIL;
-
-  temp1 = gen_reg_rtx (DImode);
-  temp2 = gen_reg_rtx (DImode);
-
-  emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
-  emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
-  emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
-  DONE;
-}")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
-		(match_operand:DI 2 "exact_log2_cint_operand" "N")))]
-  "TARGET_POWERPC64"
-  "sradi %0,%1,%p2\;addze %0,%0"
-  [(set_attr "type" "two")
-   (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-			    (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 "=r,r"))]
-  "TARGET_64BIT"
-  "@
-   sradi %3,%1,%p2\;addze. %3,%3
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "8,12")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			    (match_operand:DI 2 "exact_log2_cint_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 3)
-	(div:DI (match_dup 1) (match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-			    (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(div:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_64BIT"
-  "@
-   sradi %0,%1,%p2\;addze. %0,%0
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "8,12")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			    (match_operand:DI 2 "exact_log2_cint_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(div:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 0)
-	(div:DI (match_dup 1) (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-        (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
-                (match_operand:DI 2 "gpc_reg_operand" "r")))]
-  "TARGET_POWERPC64"
-  "divd %0,%1,%2"
-  [(set_attr "type" "ldiv")])
-
-(define_insn "udivdi3"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-        (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
-                 (match_operand:DI 2 "gpc_reg_operand" "r")))]
-  "TARGET_POWERPC64"
-  "divdu %0,%1,%2"
-  [(set_attr "type" "ldiv")])
-
 (define_insn "rotldi3"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 	(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
@@ -6221,7 +6102,7 @@
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 	(and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
 			   (match_operand:DI 2 "reg_or_cint_operand" "ri"))
-		(match_operand:DI 3 "mask64_operand" "n")))]
+		(match_operand:DI 3 "mask_operand" "n")))]
   "TARGET_POWERPC64"
   "rld%I2c%B3 %0,%1,%H2,%S3")
 
@@ -6230,7 +6111,7 @@
 	(compare:CC (and:DI
 		     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
 				(match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
-		     (match_operand:DI 3 "mask64_operand" "n,n"))
+		     (match_operand:DI 3 "mask_operand" "n,n"))
 		    (const_int 0)))
    (clobber (match_scratch:DI 4 "=r,r"))]
   "TARGET_64BIT"
@@ -6245,7 +6126,7 @@
 	(compare:CC (and:DI
 		     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
 				(match_operand:DI 2 "reg_or_cint_operand" ""))
-		     (match_operand:DI 3 "mask64_operand" ""))
+		     (match_operand:DI 3 "mask_operand" ""))
 		    (const_int 0)))
    (clobber (match_scratch:DI 4 ""))]
   "TARGET_POWERPC64 && reload_completed"
@@ -6263,7 +6144,7 @@
 	(compare:CC (and:DI
 		     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
 				(match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
-		     (match_operand:DI 3 "mask64_operand" "n,n"))
+		     (match_operand:DI 3 "mask_operand" "n,n"))
 		    (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
 	(and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
@@ -6279,7 +6160,7 @@
 	(compare:CC (and:DI
 		     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
 				(match_operand:DI 2 "reg_or_cint_operand" ""))
-		     (match_operand:DI 3 "mask64_operand" ""))
+		     (match_operand:DI 3 "mask_operand" ""))
 		    (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "")
 	(and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
@@ -6677,7 +6558,7 @@
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 	(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
 			   (match_operand:SI 2 "const_int_operand" "i"))
-		(match_operand:DI 3 "mask64_operand" "n")))]
+		(match_operand:DI 3 "mask_operand" "n")))]
   "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
   "rldicr %0,%1,%H2,%S3")
 
@@ -6686,7 +6567,7 @@
 	(compare:CC
 	 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
 			    (match_operand:SI 2 "const_int_operand" "i,i"))
-		 (match_operand:DI 3 "mask64_operand" "n,n"))
+		 (match_operand:DI 3 "mask_operand" "n,n"))
 	 (const_int 0)))
    (clobber (match_scratch:DI 4 "=r,r"))]
   "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
@@ -6701,7 +6582,7 @@
 	(compare:CC
 	 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
 			    (match_operand:SI 2 "const_int_operand" ""))
-		 (match_operand:DI 3 "mask64_operand" ""))
+		 (match_operand:DI 3 "mask_operand" ""))
 	 (const_int 0)))
    (clobber (match_scratch:DI 4 ""))]
   "TARGET_POWERPC64 && reload_completed
@@ -6719,7 +6600,7 @@
 	(compare:CC
 	 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
 			    (match_operand:SI 2 "const_int_operand" "i,i"))
-		    (match_operand:DI 3 "mask64_operand" "n,n"))
+		    (match_operand:DI 3 "mask_operand" "n,n"))
 	 (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
 	(and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
@@ -6735,7 +6616,7 @@
 	(compare:CC
 	 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
 			    (match_operand:SI 2 "const_int_operand" ""))
-		 (match_operand:DI 3 "mask64_operand" ""))
+		 (match_operand:DI 3 "mask_operand" ""))
 	 (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "")
 	(and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
@@ -6940,7 +6821,7 @@
    (clobber (match_scratch:CC 3 ""))]
   "TARGET_POWERPC64
     && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
-    && !mask64_operand (operands[2], DImode)"
+    && !mask_operand (operands[2], DImode)"
   [(set (match_dup 0)
 	(and:DI (rotate:DI (match_dup 1)
 			   (match_dup 4))
@@ -6976,23 +6857,6 @@
    (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
 
 (define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-        (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
-                            (match_operand:DI 2 "and64_operand" ""))
-                    (const_int 0)))
-   (clobber (match_scratch:DI 3 ""))
-   (clobber (match_scratch:CC 4 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(parallel [(set (match_dup 3)
-                   (and:DI (match_dup 1)
-                           (match_dup 2)))
-              (clobber (match_dup 4))])
-   (set (match_dup 0)
-        (compare:CC (match_dup 3)
-                    (const_int 0)))]
-  "")
-
-(define_split
   [(set (match_operand:CC 0 "cc_reg_operand" "")
         (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
                             (match_operand:DI 2 "mask64_2_operand" ""))
@@ -7001,7 +6865,7 @@
    (clobber (match_scratch:CC 4 ""))]
   "TARGET_POWERPC64 && reload_completed
     && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
-    && !mask64_operand (operands[2], DImode)"
+    && !mask_operand (operands[2], DImode)"
   [(set (match_dup 3)
 	(and:DI (rotate:DI (match_dup 1)
 			   (match_dup 5))
@@ -7043,7 +6907,7 @@
 (define_split
   [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
 	(compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			    (match_operand:DI 2 "and64_operand" ""))
+			    (match_operand:DI 2 "and_operand" ""))
 		    (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "")
 	(and:DI (match_dup 1) (match_dup 2)))
@@ -7067,7 +6931,7 @@
    (clobber (match_scratch:CC 4 ""))]
   "TARGET_POWERPC64 && reload_completed
     && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
-    && !mask64_operand (operands[2], DImode)"
+    && !mask_operand (operands[2], DImode)"
   [(set (match_dup 0)
 	(and:DI (rotate:DI (match_dup 1)
 			   (match_dup 5))
@@ -7445,12 +7309,6 @@
 ;; do the load 16-bits at a time.  We could do this by loading from memory,
 ;; and this is even supposed to be faster, but it is simpler not to get
 ;; integers in the TOC.
-(define_expand "movsi"
-  [(set (match_operand:SI 0 "general_operand" "")
-	(match_operand:SI 1 "any_operand" ""))]
-  ""
-  "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }")
-
 (define_insn "movsi_low"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
         (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
@@ -7504,14 +7362,14 @@
     FAIL;
 }")
 
-(define_insn "*movsi_internal2"
+(define_insn "*mov<mode>_internal2"
   [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
-	(compare:CC (match_operand:SI 1 "gpc_reg_operand" "0,r,r")
+	(compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
-  "TARGET_32BIT"
+   (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
+  ""
   "@
-   {cmpi|cmpwi} %2,%0,0
+   {cmpi|cmp<wd>i} %2,%0,0
    mr. %0,%1
    #"
   [(set_attr "type" "cmp,compare,cmp")
@@ -7519,22 +7377,16 @@
 
 (define_split
   [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
-	(compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
+	(compare:CC (match_operand:P 1 "gpc_reg_operand" "")
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))]
-  "TARGET_32BIT && reload_completed"
+   (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
+  "reload_completed"
   [(set (match_dup 0) (match_dup 1))
    (set (match_dup 2)
 	(compare:CC (match_dup 0)
 		    (const_int 0)))]
   "")
 
-(define_expand "movhi"
-  [(set (match_operand:HI 0 "general_operand" "")
-	(match_operand:HI 1 "any_operand" ""))]
-  ""
-  "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }")
-
 (define_insn "*movhi_internal"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
 	(match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
@@ -7551,11 +7403,11 @@
    {cror 0,0,0|nop}"
   [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
 
-(define_expand "movqi"
-  [(set (match_operand:QI 0 "general_operand" "")
-	(match_operand:QI 1 "any_operand" ""))]
+(define_expand "mov<mode>"
+  [(set (match_operand:INT 0 "general_operand" "")
+	(match_operand:INT 1 "any_operand" ""))]
   ""
-  "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }")
+  "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
 
 (define_insn "*movqi_internal"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
@@ -8204,11 +8056,6 @@
 
 ;; Next come the multi-word integer load and store and the load and store
 ;; multiple insns.
-(define_expand "movdi"
-  [(set (match_operand:DI 0 "general_operand" "")
-	(match_operand:DI 1 "any_operand" ""))]
-  ""
-  "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }")
 
 ; List r->r after r->"o<>", otherwise reload will try to reload a
 ; non-offsettable address by using r->r which won't make progress.
@@ -8298,7 +8145,7 @@
 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
 (define_split
   [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(match_operand:DI 1 "mask64_operand" ""))]
+	(match_operand:DI 1 "mask_operand" ""))]
   "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
   [(set (match_dup 0) (const_int -1))
    (set (match_dup 0)
@@ -8340,41 +8187,10 @@
   else
     FAIL;
 }")
-
-(define_insn "*movdi_internal2"
-  [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
-	(compare:CC (match_operand:DI 1 "gpc_reg_operand" "0,r,r")
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
-  "TARGET_64BIT"
-  "@
-   cmpdi %2,%0,0
-   mr. %0,%1
-   #"
-  [(set_attr "type" "cmp,compare,cmp")
-   (set_attr "length" "4,4,8")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
-	(compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 0) (match_dup 1))
-   (set (match_dup 2)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
 
 ;; TImode is similar, except that we usually want to compute the address into
 ;; a register and use lsi/stsi (the exception is during reload).  MQ is also
 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
-(define_expand "movti"
-  [(parallel [(set (match_operand:TI 0 "general_operand" "")
-		   (match_operand:TI 1 "general_operand" ""))
-	      (clobber (scratch:SI))])]
-  ""
-  "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }")
 
 ;; We say that MQ is clobbered in the last alternative because the first
 ;; alternative would never get used otherwise since it would need a reload
@@ -8878,8 +8694,8 @@
    (set_attr "length" "8")])
 
 (define_insn ""
-  [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
-	(mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
+  [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
+	(mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
    (use (match_operand:SI 2 "immediate_operand" "i"))
    (use (match_operand:SI 3 "immediate_operand" "i"))
    (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
@@ -8901,30 +8717,6 @@
   [(set_attr "type" "load")
    (set_attr "length" "8")])
 
-(define_insn ""
-  [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
-	(mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
-   (use (match_operand:SI 2 "immediate_operand" "i"))
-   (use (match_operand:SI 3 "immediate_operand" "i"))
-   (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
-   (clobber (reg:SI  6))
-   (clobber (reg:SI  7))
-   (clobber (reg:SI  8))
-   (clobber (reg:SI  9))
-   (clobber (reg:SI 10))
-   (clobber (reg:SI 11))
-   (clobber (reg:SI 12))
-   (clobber (match_scratch:SI 5 "X"))]
-  "TARGET_STRING && TARGET_POWERPC64
-   && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
-       || INTVAL (operands[2]) == 0)
-   && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
-   && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
-   && REGNO (operands[4]) == 5"
-  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "load")
-   (set_attr "length" "8")])
-
 ;; Move up to 24 bytes at a time.  The fixed registers are needed because the
 ;; register allocator doesn't have a clue about allocating 6 word registers.
 ;; rD/rS = r5 is preferred, efficient form.
@@ -8965,8 +8757,8 @@
    (set_attr "length" "8")])
 
 (define_insn ""
-  [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
-	(mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
+  [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
+	(mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
    (use (match_operand:SI 2 "immediate_operand" "i"))
    (use (match_operand:SI 3 "immediate_operand" "i"))
    (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
@@ -8985,27 +8777,6 @@
   [(set_attr "type" "load")
    (set_attr "length" "8")])
 
-(define_insn ""
-  [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
-	(mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
-   (use (match_operand:SI 2 "immediate_operand" "i"))
-   (use (match_operand:SI 3 "immediate_operand" "i"))
-   (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
-   (clobber (reg:SI  6))
-   (clobber (reg:SI  7))
-   (clobber (reg:SI  8))
-   (clobber (reg:SI  9))
-   (clobber (reg:SI 10))
-   (clobber (match_scratch:SI 5 "X"))]
-  "TARGET_STRING && TARGET_POWERPC64
-   && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
-   && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
-   && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
-   && REGNO (operands[4]) == 5"
-  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "load")
-   (set_attr "length" "8")])
-
 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
 ;; problems with TImode.
 ;; rD/rS = r5 is preferred, efficient form.
@@ -9042,8 +8813,8 @@
    (set_attr "length" "8")])
 
 (define_insn ""
-  [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
-	(mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
+  [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
+	(mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
    (use (match_operand:SI 2 "immediate_operand" "i"))
    (use (match_operand:SI 3 "immediate_operand" "i"))
    (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
@@ -9060,25 +8831,6 @@
   [(set_attr "type" "load")
    (set_attr "length" "8")])
 
-(define_insn ""
-  [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
-	(mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
-   (use (match_operand:SI 2 "immediate_operand" "i"))
-   (use (match_operand:SI 3 "immediate_operand" "i"))
-   (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
-   (clobber (reg:SI 6))
-   (clobber (reg:SI 7))
-   (clobber (reg:SI 8))
-   (clobber (match_scratch:SI 5 "X"))]
-  "TARGET_STRING && TARGET_POWERPC64
-   && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
-   && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
-   && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
-   && REGNO (operands[4]) == 5"
-  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "load")
-   (set_attr "length" "8")])
-
 ;; Move up to 8 bytes at a time.
 (define_expand "movmemsi_2reg"
   [(parallel [(set (match_operand 0 "" "")
@@ -9141,8 +8893,8 @@
    (set_attr "length" "8")])
 
 (define_insn ""
-  [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
-	(mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
+  [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
+	(mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
    (use (match_operand:SI 2 "immediate_operand" "i"))
    (use (match_operand:SI 3 "immediate_operand" "i"))
    (clobber (match_scratch:SI 4 "=&r"))
@@ -9152,20 +8904,6 @@
   "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
   [(set_attr "type" "load")
    (set_attr "length" "8")])
-
-(define_insn ""
-  [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
-	(mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
-   (use (match_operand:SI 2 "immediate_operand" "i"))
-   (use (match_operand:SI 3 "immediate_operand" "i"))
-   (clobber (match_scratch:SI 4 "=&r"))
-   (clobber (match_scratch:SI 5 "X"))]
-  "TARGET_STRING && TARGET_POWERPC64
-   && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
-  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
-  [(set_attr "type" "load")
-   (set_attr "length" "8")])
-
 
 ;; Define insns that do load or store with update.  Some of these we can
 ;; get by using pre-decrement or pre-increment, but the hardware can also
@@ -10762,10 +10500,10 @@
 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
 ;; insns, and branches.  We store the operands of compares until we see
 ;; how it is used.
-(define_expand "cmpsi"
+(define_expand "cmp<mode>"
   [(set (cc0)
-        (compare (match_operand:SI 0 "gpc_reg_operand" "")
-  		 (match_operand:SI 1 "reg_or_short_operand" "")))]
+        (compare (match_operand:GPR 0 "gpc_reg_operand" "")
+  		 (match_operand:GPR 1 "reg_or_short_operand" "")))]
   ""
   "
 {
@@ -10773,26 +10511,7 @@
      this might be a logical operation.  That insn doesn't exist.  */
   if (GET_CODE (operands[1]) == CONST_INT
       && INTVAL (operands[1]) < 0)
-    operands[1] = force_reg (SImode, operands[1]);
-
-  rs6000_compare_op0 = operands[0];
-  rs6000_compare_op1 = operands[1];
-  rs6000_compare_fp_p = 0;
-  DONE;
-}")
-
-(define_expand "cmpdi"
-  [(set (cc0)
-        (compare (match_operand:DI 0 "gpc_reg_operand" "")
-  		 (match_operand:DI 1 "reg_or_short_operand" "")))]
-  "TARGET_POWERPC64"
-  "
-{
-  /* Take care of the possibility that operands[1] might be negative but
-     this might be a logical operation.  That insn doesn't exist.  */
-  if (GET_CODE (operands[1]) == CONST_INT
-      && INTVAL (operands[1]) < 0)
-    operands[1] = force_reg (DImode, operands[1]);
+    operands[1] = force_reg (<MODE>mode, operands[1]);
 
   rs6000_compare_op0 = operands[0];
   rs6000_compare_op1 = operands[1];
@@ -10800,35 +10519,10 @@
   DONE;
 }")
 
-(define_expand "cmpsf"
-  [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
-		       (match_operand:SF 1 "gpc_reg_operand" "")))]
-  "TARGET_HARD_FLOAT"
-  "
-{
-  rs6000_compare_op0 = operands[0];
-  rs6000_compare_op1 = operands[1];
-  rs6000_compare_fp_p = 1;
-  DONE;
-}")
-
-(define_expand "cmpdf"
-  [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
-		       (match_operand:DF 1 "gpc_reg_operand" "")))]
-  "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
-  "
-{
-  rs6000_compare_op0 = operands[0];
-  rs6000_compare_op1 = operands[1];
-  rs6000_compare_fp_p = 1;
-  DONE;
-}")
-
-(define_expand "cmptf"
-  [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "")
-		       (match_operand:TF 1 "gpc_reg_operand" "")))]
-  "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
-   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
+(define_expand "cmp<mode>"
+  [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
+		       (match_operand:FP 1 "gpc_reg_operand" "")))]
+  ""
   "
 {
   rs6000_compare_op0 = operands[0];
@@ -11063,20 +10757,12 @@
 
 
 ;; Here are the actual compare insns.
-(define_insn "*cmpsi_internal1"
+(define_insn "*cmp<mode>_internal1"
   [(set (match_operand:CC 0 "cc_reg_operand" "=y")
-	(compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
-		    (match_operand:SI 2 "reg_or_short_operand" "rI")))]
+	(compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
+		    (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
   ""
-  "{cmp%I2|cmpw%I2} %0,%1,%2"
-  [(set_attr "type" "cmp")])
-
-(define_insn "*cmpdi_internal1"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
-	(compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
-		    (match_operand:DI 2 "reg_or_short_operand" "rI")))]
-  "TARGET_POWERPC64"
-  "cmpd%I2 %0,%1,%2"
+  "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
   [(set_attr "type" "cmp")])
 
 ;; If we are comparing a register for equality with a large constant,
@@ -13765,33 +13451,16 @@
   [(set_attr "type" "jmpreg")])
 
 (define_expand "indirect_jump"
-  [(set (pc) (match_operand 0 "register_operand" ""))]
-  ""
-  "
-{
-  if (TARGET_32BIT)
-    emit_jump_insn (gen_indirect_jumpsi (operands[0]));
-  else
-    emit_jump_insn (gen_indirect_jumpdi (operands[0]));
-  DONE;
-}")
+  [(set (pc) (match_operand 0 "register_operand" ""))])
 
-(define_insn "indirect_jumpsi"
-  [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))]
-  "TARGET_32BIT"
+(define_insn "*indirect_jump<mode>"
+  [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
+  ""
   "@
    bctr
    {br|blr}"
   [(set_attr "type" "jmpreg")])
 
-(define_insn "indirect_jumpdi"
-  [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))]
-  "TARGET_64BIT"
-  "@
-   bctr
-   blr"
-  [(set_attr "type" "jmpreg")])
-
 ;; Table jump for switch statements:
 (define_expand "tablejump"
   [(use (match_operand 0 "" ""))
@@ -13836,24 +13505,14 @@
 
 (define_insn ""
   [(set (pc)
-	(match_operand:SI 0 "register_operand" "c,*l"))
+	(match_operand:P 0 "register_operand" "c,*l"))
    (use (label_ref (match_operand 1 "" "")))]
-  "TARGET_32BIT"
+  ""
   "@
    bctr
    {br|blr}"
   [(set_attr "type" "jmpreg")])
 
-(define_insn ""
-  [(set (pc)
-	(match_operand:DI 0 "register_operand" "c,*l"))
-   (use (label_ref (match_operand 1 "" "")))]
-  "TARGET_64BIT"
-  "@
-   bctr
-   blr"
-  [(set_attr "type" "jmpreg")])
-
 (define_insn "nop"
   [(const_int 0)]
   ""
@@ -13889,32 +13548,18 @@
   DONE;
 }")
 
-(define_expand "ctrsi"
+(define_expand "ctr<mode>"
   [(parallel [(set (pc)
-		   (if_then_else (ne (match_operand:SI 0 "register_operand" "")
+		   (if_then_else (ne (match_operand:P 0 "register_operand" "")
 				     (const_int 1))
 				 (label_ref (match_operand 1 "" ""))
 				 (pc)))
 	      (set (match_dup 0)
-		   (plus:SI (match_dup 0)
+		   (plus:P (match_dup 0)
 			    (const_int -1)))
 	      (clobber (match_scratch:CC 2 ""))
-	      (clobber (match_scratch:SI 3 ""))])]
-  "TARGET_32BIT"
-  "")
-
-(define_expand "ctrdi"
-  [(parallel [(set (pc)
-		   (if_then_else (ne (match_operand:DI 0 "register_operand" "")
-				     (const_int 1))
-				 (label_ref (match_operand 1 "" ""))
-				 (pc)))
-	      (set (match_dup 0)
-		   (plus:DI (match_dup 0)
-			    (const_int -1)))
-	      (clobber (match_scratch:CC 2 ""))
-	      (clobber (match_scratch:DI 3 ""))])]
-  "TARGET_64BIT"
+	      (clobber (match_scratch:P 3 ""))])]
+  ""
   "")
 
 ;; We need to be able to do this for any operand, including MEM, or we
@@ -13923,66 +13568,18 @@
 ;; For the length attribute to be calculated correctly, the
 ;; label MUST be operand 0.
 
-(define_insn "*ctrsi_internal1"
-  [(set (pc)
-	(if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
-			  (const_int 1))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))
-   (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
-	(plus:SI (match_dup 1)
-		 (const_int -1)))
-   (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
-   (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
-  "TARGET_32BIT"
-  "*
-{
-  if (which_alternative != 0)
-    return \"#\";
-  else if (get_attr_length (insn) == 4)
-    return \"{bdn|bdnz} %l0\";
-  else
-    return \"bdz $+8\;b %l0\";
-}"
-  [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16,16")])
-
-(define_insn "*ctrsi_internal2"
-  [(set (pc)
-	(if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
-			  (const_int 1))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))
-   (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
-	(plus:SI (match_dup 1)
-		 (const_int -1)))
-   (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
-   (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
-  "TARGET_32BIT"
-  "*
-{
-  if (which_alternative != 0)
-    return \"#\";
-  else if (get_attr_length (insn) == 4)
-    return \"bdz %l0\";
-  else
-    return \"{bdn|bdnz} $+8\;b %l0\";
-}"
-  [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16,16")])
-
-(define_insn "*ctrdi_internal1"
+(define_insn "*ctr<mode>_internal1"
   [(set (pc)
-	(if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
+	(if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
 			  (const_int 1))
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))
-   (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
-	(plus:DI (match_dup 1)
+   (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
+	(plus:P (match_dup 1)
 		 (const_int -1)))
    (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
-   (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
-  "TARGET_64BIT"
+   (clobber (match_scratch:P 4 "=X,X,&r,r"))]
+  ""
   "*
 {
   if (which_alternative != 0)
@@ -13995,18 +13592,18 @@
   [(set_attr "type" "branch")
    (set_attr "length" "*,12,16,16")])
 
-(define_insn "*ctrdi_internal2"
+(define_insn "*ctr<mode>_internal2"
   [(set (pc)
-	(if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
+	(if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
 			  (const_int 1))
 		      (pc)
 		      (label_ref (match_operand 0 "" ""))))
-   (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
-	(plus:DI (match_dup 1)
+   (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
+	(plus:P (match_dup 1)
 		 (const_int -1)))
    (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
-   (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
-  "TARGET_64BIT"
+   (clobber (match_scratch:P 4 "=X,X,&r,r"))]
+  ""
   "*
 {
   if (which_alternative != 0)
@@ -14021,66 +13618,18 @@
 
 ;; Similar but use EQ
 
-(define_insn "*ctrsi_internal5"
-  [(set (pc)
-	(if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
-			  (const_int 1))
-		      (label_ref (match_operand 0 "" ""))
-		      (pc)))
-   (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
-	(plus:SI (match_dup 1)
-		 (const_int -1)))
-   (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
-   (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
-  "TARGET_32BIT"
-  "*
-{
-  if (which_alternative != 0)
-    return \"#\";
-  else if (get_attr_length (insn) == 4)
-    return \"bdz %l0\";
-  else
-    return \"{bdn|bdnz} $+8\;b %l0\";
-}"
-  [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16,16")])
-
-(define_insn "*ctrsi_internal6"
+(define_insn "*ctr<mode>_internal5"
   [(set (pc)
-	(if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
-			  (const_int 1))
-		      (pc)
-		      (label_ref (match_operand 0 "" ""))))
-   (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
-	(plus:SI (match_dup 1)
-		 (const_int -1)))
-   (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
-   (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
-  "TARGET_32BIT"
-  "*
-{
-  if (which_alternative != 0)
-    return \"#\";
-  else if (get_attr_length (insn) == 4)
-    return \"{bdn|bdnz} %l0\";
-  else
-    return \"bdz $+8\;b %l0\";
-}"
-  [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16,16")])
-
-(define_insn "*ctrdi_internal5"
-  [(set (pc)
-	(if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
+	(if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
 			  (const_int 1))
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))
-   (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
-	(plus:DI (match_dup 1)
+   (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
+	(plus:P (match_dup 1)
 		 (const_int -1)))
    (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
-   (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
-  "TARGET_64BIT"
+   (clobber (match_scratch:P 4 "=X,X,&r,r"))]
+  ""
   "*
 {
   if (which_alternative != 0)
@@ -14093,18 +13642,18 @@
   [(set_attr "type" "branch")
    (set_attr "length" "*,12,16,16")])
 
-(define_insn "*ctrdi_internal6"
+(define_insn "*ctr<mode>_internal6"
   [(set (pc)
-	(if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
+	(if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
 			  (const_int 1))
 		      (pc)
 		      (label_ref (match_operand 0 "" ""))))
-   (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
-	(plus:DI (match_dup 1)
+   (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
+	(plus:P (match_dup 1)
 		 (const_int -1)))
    (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
-   (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
-  "TARGET_64BIT"
+   (clobber (match_scratch:P 4 "=X,X,&r,r"))]
+  ""
   "*
 {
   if (which_alternative != 0)
@@ -14122,77 +13671,21 @@
 (define_split
   [(set (pc)
 	(if_then_else (match_operator 2 "comparison_operator"
-				      [(match_operand:SI 1 "gpc_reg_operand" "")
-				       (const_int 1)])
-		      (match_operand 5 "" "")
-		      (match_operand 6 "" "")))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(plus:SI (match_dup 1)
-		 (const_int -1)))
-   (clobber (match_scratch:CC 3 ""))
-   (clobber (match_scratch:SI 4 ""))]
-  "TARGET_32BIT && reload_completed"
-  [(parallel [(set (match_dup 3)
-		   (compare:CC (plus:SI (match_dup 1)
-					(const_int -1))
-			       (const_int 0)))
-	      (set (match_dup 0)
-		   (plus:SI (match_dup 1)
-			    (const_int -1)))])
-   (set (pc) (if_then_else (match_dup 7)
-			   (match_dup 5)
-			   (match_dup 6)))]
-  "
-{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
-				operands[3], const0_rtx); }")
-
-(define_split
-  [(set (pc)
-	(if_then_else (match_operator 2 "comparison_operator"
-				      [(match_operand:SI 1 "gpc_reg_operand" "")
+				      [(match_operand:P 1 "gpc_reg_operand" "")
 				       (const_int 1)])
 		      (match_operand 5 "" "")
 		      (match_operand 6 "" "")))
-   (set (match_operand:SI 0 "nonimmediate_operand" "")
-	(plus:SI (match_dup 1) (const_int -1)))
-   (clobber (match_scratch:CC 3 ""))
-   (clobber (match_scratch:SI 4 ""))]
-  "TARGET_32BIT && reload_completed
-   && ! gpc_reg_operand (operands[0], SImode)"
-  [(parallel [(set (match_dup 3)
-		   (compare:CC (plus:SI (match_dup 1)
-					(const_int -1))
-			       (const_int 0)))
-	      (set (match_dup 4)
-		   (plus:SI (match_dup 1)
-			    (const_int -1)))])
-   (set (match_dup 0)
-	(match_dup 4))
-   (set (pc) (if_then_else (match_dup 7)
-			   (match_dup 5)
-			   (match_dup 6)))]
-  "
-{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
-				operands[3], const0_rtx); }")
-(define_split
-  [(set (pc)
-	(if_then_else (match_operator 2 "comparison_operator"
-				      [(match_operand:DI 1 "gpc_reg_operand" "")
-				       (const_int 1)])
-		      (match_operand 5 "" "")
-		      (match_operand 6 "" "")))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(plus:DI (match_dup 1)
-		 (const_int -1)))
+   (set (match_operand:P 0 "gpc_reg_operand" "")
+	(plus:P (match_dup 1) (const_int -1)))
    (clobber (match_scratch:CC 3 ""))
-   (clobber (match_scratch:DI 4 ""))]
-  "TARGET_64BIT && reload_completed"
+   (clobber (match_scratch:P 4 ""))]
+  "reload_completed"
   [(parallel [(set (match_dup 3)
-		   (compare:CC (plus:DI (match_dup 1)
+		   (compare:CC (plus:P (match_dup 1)
 					(const_int -1))
 			       (const_int 0)))
 	      (set (match_dup 0)
-		   (plus:DI (match_dup 1)
+		   (plus:P (match_dup 1)
 			    (const_int -1)))])
    (set (pc) (if_then_else (match_dup 7)
 			   (match_dup 5)
@@ -14204,22 +13697,21 @@
 (define_split
   [(set (pc)
 	(if_then_else (match_operator 2 "comparison_operator"
-				      [(match_operand:DI 1 "gpc_reg_operand" "")
+				      [(match_operand:P 1 "gpc_reg_operand" "")
 				       (const_int 1)])
 		      (match_operand 5 "" "")
 		      (match_operand 6 "" "")))
-   (set (match_operand:DI 0 "nonimmediate_operand" "")
-	(plus:DI (match_dup 1) (const_int -1)))
+   (set (match_operand:P 0 "nonimmediate_operand" "")
+	(plus:P (match_dup 1) (const_int -1)))
    (clobber (match_scratch:CC 3 ""))
-   (clobber (match_scratch:DI 4 ""))]
-  "TARGET_64BIT && reload_completed
-   && ! gpc_reg_operand (operands[0], DImode)"
+   (clobber (match_scratch:P 4 ""))]
+  "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
   [(parallel [(set (match_dup 3)
-		   (compare:CC (plus:DI (match_dup 1)
+		   (compare:CC (plus:P (match_dup 1)
 					(const_int -1))
 			       (const_int 0)))
 	      (set (match_dup 4)
-		   (plus:DI (match_dup 1)
+		   (plus:P (match_dup 1)
 			    (const_int -1)))])
    (set (match_dup 0)
 	(match_dup 4))
@@ -14246,19 +13738,11 @@
 
 (define_insn ""
   [(trap_if (match_operator 0 "trap_comparison_operator"
-                            [(match_operand:SI 1 "register_operand" "r")
-                             (match_operand:SI 2 "reg_or_short_operand" "rI")])
+                            [(match_operand:GPR 1 "register_operand" "r")
+                             (match_operand:GPR 2 "reg_or_short_operand" "rI")])
 	    (const_int 0))]
   ""
-  "{t|tw}%V0%I2 %1,%2")
-
-(define_insn ""
-  [(trap_if (match_operator 0 "trap_comparison_operator"
-                            [(match_operand:DI 1 "register_operand" "r")
-                             (match_operand:DI 2 "reg_or_short_operand" "rI")])
-	    (const_int 0))]
-  "TARGET_POWERPC64"
-  "td%V0%I2 %1,%2")
+  "{t|t<wd>}%V0%I2 %1,%2")
 
 ;; Insns related to generating the function prologue and epilogue.
 
@@ -14308,24 +13792,13 @@
   "TARGET_MULTIPLE"
   "{stm|stmw} %2,%1")
 
-(define_insn "*save_fpregs_si"
+(define_insn "*save_fpregs_<mode>"
   [(match_parallel 0 "any_parallel_operand"
-		   [(clobber (match_operand:SI 1 "register_operand" "=l"))
-		    (use (match_operand:SI 2 "call_operand" "s"))
+		   [(clobber (match_operand:P 1 "register_operand" "=l"))
+		    (use (match_operand:P 2 "call_operand" "s"))
 		    (set (match_operand:DF 3 "memory_operand" "=m")
 			 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
-  "TARGET_32BIT"
-  "bl %z2"
-  [(set_attr "type" "branch")
-   (set_attr "length" "4")])
-
-(define_insn "*save_fpregs_di"
-  [(match_parallel 0 "any_parallel_operand"
-		   [(clobber (match_operand:DI 1 "register_operand" "=l"))
-		    (use (match_operand:DI 2 "call_operand" "s"))
-		    (set (match_operand:DF 3 "memory_operand" "=m")
-			 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
-  "TARGET_64BIT"
+  ""
   "bl %z2"
   [(set_attr "type" "branch")
    (set_attr "length" "4")])
@@ -14401,41 +13874,24 @@
   "TARGET_MULTIPLE"
   "{lm|lmw} %1,%2")
 
-(define_insn "*return_internal_si"
-  [(return)
-   (use (match_operand:SI 0 "register_operand" "lc"))]
-  "TARGET_32BIT"
-  "b%T0"
-  [(set_attr "type" "jmpreg")])
-
-(define_insn "*return_internal_di"
+(define_insn "*return_internal_<mode>"
   [(return)
-   (use (match_operand:DI 0 "register_operand" "lc"))]
-  "TARGET_64BIT"
+   (use (match_operand:P 0 "register_operand" "lc"))]
+  ""
   "b%T0"
   [(set_attr "type" "jmpreg")])
 
 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
 ; stuff was in GCC.  Oh, and "any_parallel_operand" is a bit flexible...
 
-(define_insn "*return_and_restore_fpregs_si"
- [(match_parallel 0 "any_parallel_operand"
-                  [(return)
-		   (use (match_operand:SI 1 "register_operand" "l"))
-		   (use (match_operand:SI 2 "call_operand" "s"))
-		   (set (match_operand:DF 3 "gpc_reg_operand" "=f")
-			(match_operand:DF 4 "memory_operand" "m"))])]
- "TARGET_32BIT"
- "b %z2")
-
-(define_insn "*return_and_restore_fpregs_di"
+(define_insn "*return_and_restore_fpregs_<mode>"
  [(match_parallel 0 "any_parallel_operand"
                   [(return)
-		   (use (match_operand:DI 1 "register_operand" "l"))
-		   (use (match_operand:DI 2 "call_operand" "s"))
+		   (use (match_operand:P 1 "register_operand" "l"))
+		   (use (match_operand:P 2 "call_operand" "s"))
 		   (set (match_operand:DF 3 "gpc_reg_operand" "=f")
 			(match_operand:DF 4 "memory_operand" "m"))])]
- "TARGET_64BIT"
+ ""
  "b %z2")
 
 ; This is used in compiling the unwind routines.
@@ -14452,18 +13908,11 @@
 }")
 
 ; We can't expand this before we know where the link register is stored.
-(define_insn "eh_set_lr_si"
-  [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
+(define_insn "eh_set_lr_<mode>"
+  [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
   		    UNSPECV_EH_RR)
-   (clobber (match_scratch:SI 1 "=&b"))]
-  "TARGET_32BIT"
-  "#")
-
-(define_insn "eh_set_lr_di"
-  [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
-  		    UNSPECV_EH_RR)
-   (clobber (match_scratch:DI 1 "=&b"))]
-  "TARGET_64BIT"
+   (clobber (match_scratch:P 1 "=&b"))]
+  ""
   "#")
 
 (define_split