Avoid problems with reloading fpul in HImode

From-SVN: r36499

5 files changed, 27 insertions, 5 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index bb20cc9..11ce53b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -3,6 +3,12 @@
 	* reload1.c (forget_old_reloads_1): If a hard reg is stored, clear
 	its entry in spill_reg_store.
 	* config/sh/lib1funcs.ams (movstr_i4 functions): Always compile in.
+	* sh.c (reg_no_subreg_operand): New function.
+	* sh-protos.h (reg_no_subreg_operand): Declare it.
+	* sh.h (PREDICATE_CODES): Add it.
+	* sh.md (floatsisf2_i4, floatsidf2_i, extendsfdf2_i4): Use it for
+	input operand that needs to be in fpul.
+	(fix_truncsfsi2, fix_truncsfsi2_i4): Use register_operand for output.
 
 2000-09-18  Alexandre Oliva  <aoliva@redhat.com>
 
diff --git a/gcc/config/sh/sh-protos.h b/gcc/config/sh/sh-protos.h
index e62edf4..e643d08 100644
--- a/gcc/config/sh/sh-protos.h
+++ b/gcc/config/sh/sh-protos.h
@@ -81,6 +81,7 @@ extern int system_reg_operand PARAMS ((rtx, enum machine_mode));
 extern int general_movsrc_operand PARAMS ((rtx, enum machine_mode));
 extern int general_movdst_operand PARAMS ((rtx, enum machine_mode));
 extern int arith_reg_operand PARAMS ((rtx, enum machine_mode));
+extern int reg_no_subreg_operand PARAMS ((rtx, enum machine_mode));
 extern int fp_arith_reg_operand PARAMS ((rtx, enum machine_mode));
 extern int fp_extended_operand PARAMS ((rtx, enum machine_mode));
 extern int arith_operand PARAMS ((rtx, enum machine_mode));
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index 1807916..bd2a382 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -4645,6 +4645,20 @@ general_movdst_operand (op, mode)
   return general_operand (op, mode);
 }
 
+/* Accept a register, but not a subreg of any kind.  This allows us to
+   avoid pathological cases in reload wrt data movement common in 
+   int->fp conversion.  */
+
+int
+reg_no_subreg_operand (op, mode)
+     register rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) == SUBREG)
+    return 0;
+  return register_operand (op, mode);
+}
+
 /* Returns 1 if OP is a normal arithmetic register.  */
 
 int
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index 1723634..eac8128 100644
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -2231,6 +2231,7 @@ extern struct rtx_def *fpscr_rtx;
 #define PREDICATE_CODES \
   {"arith_operand", {SUBREG, REG, CONST_INT}},				\
   {"arith_reg_operand", {SUBREG, REG}},					\
+  {"reg_no_subreg_operand", {REG}},					\
   {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT}},			\
   {"binary_float_operator", {PLUS, MULT}},				\
   {"commutative_float_operator", {PLUS, MULT}},				\
diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index 2930b7c..59ec818 100644
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -4235,7 +4235,7 @@ else
 
 (define_insn "floatsisf2_i4"
   [(set (match_operand:SF 0 "arith_reg_operand" "=f")
-	(float:SF (match_operand:SI 1 "register_operand" "y")))
+	(float:SF (match_operand:SI 1 "reg_no_subreg_operand" "y")))
    (use (match_operand:PSI 2 "fpscr_operand" "c"))]
   "TARGET_SH3E"
   "float	%1,%0"
@@ -4251,7 +4251,7 @@ else
 ;;  [(set_attr "type" "fp")])
 
 (define_expand "fix_truncsfsi2"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=y")
+  [(set (match_operand:SI 0 "register_operand" "=y")
 	(fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))]
   "TARGET_SH3E"
   "
@@ -4264,7 +4264,7 @@ else
 }")
 
 (define_insn "fix_truncsfsi2_i4"
-  [(set (match_operand:SI 0 "arith_reg_operand" "=y")
+  [(set (match_operand:SI 0 "register_operand" "=y")
 	(fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
    (use (match_operand:PSI 2 "fpscr_operand" "c"))]
   "TARGET_SH4"
@@ -4490,7 +4490,7 @@ else
 
 (define_insn "floatsidf2_i"
   [(set (match_operand:DF 0 "arith_reg_operand" "=f")
-	(float:DF (match_operand:SI 1 "register_operand" "y")))
+	(float:DF (match_operand:SI 1 "reg_no_subreg_operand" "y")))
    (use (match_operand:PSI 2 "fpscr_operand" "c"))]
   "TARGET_SH4"
   "float	%1,%0"
@@ -4634,7 +4634,7 @@ else
 
 (define_insn "extendsfdf2_i4"
   [(set (match_operand:DF 0 "arith_reg_operand" "=f")
-	(float_extend:DF (match_operand:SF 1 "register_operand" "y")))
+	(float_extend:DF (match_operand:SF 1 "reg_no_subreg_operand" "y")))
    (use (match_operand:PSI 2 "fpscr_operand" "c"))]
   "TARGET_SH4"
   "fcnvsd  %1,%0"