diff options
author | Hans-Peter Nilsson <hp@axis.com> | 2005-05-17 06:37:06 +0000 |
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committer | Hans-Peter Nilsson <hp@gcc.gnu.org> | 2005-05-17 06:37:06 +0000 |
commit | 22c3c0917f67402389deb1e877c429f93a6a0b38 (patch) | |
tree | f0e1c7d54615fa8e9f75b008af92b3848edf51f7 /gcc | |
parent | b96917bffef6c486ceedbc93d994e2016e070e30 (diff) | |
download | gcc-22c3c0917f67402389deb1e877c429f93a6a0b38.zip gcc-22c3c0917f67402389deb1e877c429f93a6a0b38.tar.gz gcc-22c3c0917f67402389deb1e877c429f93a6a0b38.tar.bz2 |
cris.md: Unquote preparation and output statements.
* config/cris/cris.md: Unquote preparation and output statements.
(BWD, WD, BW): New, mode-macros.
(S, s, m, mm, nbitsm1): New, mode-attrs.
(szext, shift, shiftrt, ncond, ocond, rcond): New, code-macros.
(u, su, shlr, slr, ncond, ocond, rcond, rCC, oCC, roCC): New,
code-attrs.
("tst<mode>"): Replace "tstqi", "tsthi" and "tstsi".
("*cmp_ext<mode>"): Replace "*cmp_extsi" and "*cmp_exthi".
("*cmp_swapext<mode>"): Replace "*cmp_swapextqi" and
"*cmp_swapexthi".
("cmp<mode>"): Replace "cmphi" and "cmpqi".
("movdi"): Move misplaced head comment regarding necessity of
movdi from movsi to here.
("*mov_side<mode>_biap"): Replace "*mov_sideqi_biap" and
"*mov_sidehi_biap".
("*mov_side<mode>"): Replace "*mov_sideqi" and "*mov_sidehi".
("*mov_side<mode>_biap_mem", "*mov_sidehi_biap_mem"): Replace
"*mov_sideqi_biap_mem".
("*mov_side<mode>_mem"): Replace "*mov_sideqi_mem" and
"*mov_sidehi_mem".
("*clear_side<mode>_biap"): Replace "*clear_sidesi_biap",
"*clear_sidehi_biap" and "*clear_sideqi_biap".
("*clear_side<mode>"): Replace "*clear_sidesi", "*clear_sidehi"
and "*clear_sideqi".
("*ext_side<mode>si_biap"): Replace "*ext_sideqisi_biap" and
"*ext_sidehisi_biap".
("*ext_side<mode>si"): Replace "*ext_sideqisi" and
"*ext_sidehisi".
("reload_in<mode>"): Replace "reload_inhi" and "reload_inqi".
("reload_out<mode>"): Replace "reload_outhi" and "reload_outqi".
("extend<mode>di2"): Replace "extendhidi2" and "extendqidi2".
("extend<mode>si2"): Replace "extendhisi2" and "extendqisi2".
("zero_extend<mode>si2"): Replace "zero_extendhisi2" and
"zero_extendqisi2".
("*op_side<mode>_biap"): Replace "*op_sideqi_biap",
"*op_sidehi_biap" and "*op_sidesi_biap".
("*op_side<mode>"): Replace "*op_sideqi", "*op_sidehi" and
"*op_sidesi".
("*op_swap_side<mode>_biap"): Replace "*op_swap_sideqi_biap",
"*op_swap_sidehi_biap" and "*op_swap_sidesi_biap".
("*op_swap_side<mode>"): Replace "*op_swap_sideqi",
"*op_swap_sidehi" and "*op_swap_sidesi".
("sub<mode>3"): Replace "subhi3" and "subqi3", correcting a typo
in the N alternative of "subqi3".
("*extop<mode>si_side_biap"): Replace "*extopqisi_side_biap" and
"*extophisi_side_biap".
("*extop<mode>si_side"): Replace "*extopqisi_side" and
"*extophisi_side".
("*extop<mode>si_swap_side_biap"): Replace
"*extopqisi_swap_side_biap" and "*extophisi_swap_side_biap".
("*extop<mode>si_swap_side"): Replace "*extopqisi_swap_side" and
"*extophisi_swap_side".
("*extop<mode>si"): Replace "*extopqisi" and "*extophisi".
("*extop<mode>si_swap"): Replace "*extopqisi_swap" and
"*extophisi_swap".
("<u>mul<s><mode>3"): Replace "umulhisi3", "umulqihi3",
"mulqihi3", "mulhisi3" and "mulhisi3".
("<u>mulsidi3"): Replace "mulsidi3" and "umulsidi3".
("<su>mulsi3_highpart"): Replace "smulsi3_highpart" and
"umulsi3_highpart".
("xor<mode>3"): Replace "xorhi3" and "xorqi3".
("neg<mode>2"): Replace "negsi2", "neghi2" and "negqi2".
("one_cmpl<mode>2"): Replace "one_cmplhi2" and "one_cmplqi2".
("<shlr>si3"): Replace "ashrsi3", "lshrsi3" and "ashlsi3".
("ashr<mode>3"): Replace "ashrhi3" and "ashrqi3".
("*expanded_<shlr><mode>"): Replace "*expanded_ashrhi",
"*expanded_ashrqi", "*expanded_lshrhi" and "*expanded_lshrqi".
("*<shlr><mode>_lowpart"): Replace "*ashrhi_lowpart",
"*ashrqi_lowpart", "*lshrhi_lowpart" and "*lshrqi_lowpart".
("lshr<mode>3"): Replace "lshrhi3" and "lshrqi3".
("ashl<mode>3"): Replace "ashlhi3" and "ashlqi3".
("*ashl<mode>_lowpart"): Replace "*ashlqi_lowpart" and
"*ashlhi_lowpart".
("abs<mode>2"): Replace "abshi2" and "absqi2".
("b<ncond>"): Replace "beq", "bne", "bgtu", "bltu", "bgeu" and
"bleu".
("b<ocond>"): Replace "bgt" and "ble".
("b<rcond>"): Replace "blt" and "bge".
("*b<ncond>_reversed"): Replace "*beq_reversed", "*bne_reversed",
"*bgtu_reversed", "*bltu_reversed", "*bgeu_reversed" and
"*bleu_reversed".
("*b<ocond>_reversed"): Replace "*bgt_reversed" and
"*ble_reversed".
("*b<rcond>_reversed"): Replace "*blt_reversed" and
"*blt_reversed".
("s<ncond>"): Replace "sgeu", "sltu", "seq", "sgtu", "sleu" and
"sne".
("s<rcond>"): Replace "sge" and "slt".
("s<ocond>"): Replace "sgt" and "sle".
("clear.[bwd] [rx=rx+rz.S2]"): Replace split clear.d
[rx=rx+rz.S2], clear.w [rx=rx+rz.S2] and clear.b [rx=rx+rz.S2].
("clear.[bwd] [rx=rx+i]"): Replace splits clear.d [rx=rx+i],
clear.w [rx=rx+i] and clear.b [rx=rx+i].
From-SVN: r99814
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/ChangeLog | 96 | ||||
-rw-r--r-- | gcc/config/cris/cris.md | 2032 |
2 files changed, 494 insertions, 1634 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8ba8ea9..7bab281 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,99 @@ +2005-05-17 Hans-Peter Nilsson <hp@axis.com> + + * config/cris/cris.md: Unquote preparation and output statements. + (BWD, WD, BW): New, mode-macros. + (S, s, m, mm, nbitsm1): New, mode-attrs. + (szext, shift, shiftrt, ncond, ocond, rcond): New, code-macros. + (u, su, shlr, slr, ncond, ocond, rcond, rCC, oCC, roCC): New, + code-attrs. + ("tst<mode>"): Replace "tstqi", "tsthi" and "tstsi". + ("*cmp_ext<mode>"): Replace "*cmp_extsi" and "*cmp_exthi". + ("*cmp_swapext<mode>"): Replace "*cmp_swapextqi" and + "*cmp_swapexthi". + ("cmp<mode>"): Replace "cmphi" and "cmpqi". + ("movdi"): Move misplaced head comment regarding necessity of + movdi from movsi to here. + ("*mov_side<mode>_biap"): Replace "*mov_sideqi_biap" and + "*mov_sidehi_biap". + ("*mov_side<mode>"): Replace "*mov_sideqi" and "*mov_sidehi". + ("*mov_side<mode>_biap_mem", "*mov_sidehi_biap_mem"): Replace + "*mov_sideqi_biap_mem". + ("*mov_side<mode>_mem"): Replace "*mov_sideqi_mem" and + "*mov_sidehi_mem". + ("*clear_side<mode>_biap"): Replace "*clear_sidesi_biap", + "*clear_sidehi_biap" and "*clear_sideqi_biap". + ("*clear_side<mode>"): Replace "*clear_sidesi", "*clear_sidehi" + and "*clear_sideqi". + ("*ext_side<mode>si_biap"): Replace "*ext_sideqisi_biap" and + "*ext_sidehisi_biap". + ("*ext_side<mode>si"): Replace "*ext_sideqisi" and + "*ext_sidehisi". + ("reload_in<mode>"): Replace "reload_inhi" and "reload_inqi". + ("reload_out<mode>"): Replace "reload_outhi" and "reload_outqi". + ("extend<mode>di2"): Replace "extendhidi2" and "extendqidi2". + ("extend<mode>si2"): Replace "extendhisi2" and "extendqisi2". + ("zero_extend<mode>si2"): Replace "zero_extendhisi2" and + "zero_extendqisi2". + ("*op_side<mode>_biap"): Replace "*op_sideqi_biap", + "*op_sidehi_biap" and "*op_sidesi_biap". + ("*op_side<mode>"): Replace "*op_sideqi", "*op_sidehi" and + "*op_sidesi". + ("*op_swap_side<mode>_biap"): Replace "*op_swap_sideqi_biap", + "*op_swap_sidehi_biap" and "*op_swap_sidesi_biap". + ("*op_swap_side<mode>"): Replace "*op_swap_sideqi", + "*op_swap_sidehi" and "*op_swap_sidesi". + ("sub<mode>3"): Replace "subhi3" and "subqi3", correcting a typo + in the N alternative of "subqi3". + ("*extop<mode>si_side_biap"): Replace "*extopqisi_side_biap" and + "*extophisi_side_biap". + ("*extop<mode>si_side"): Replace "*extopqisi_side" and + "*extophisi_side". + ("*extop<mode>si_swap_side_biap"): Replace + "*extopqisi_swap_side_biap" and "*extophisi_swap_side_biap". + ("*extop<mode>si_swap_side"): Replace "*extopqisi_swap_side" and + "*extophisi_swap_side". + ("*extop<mode>si"): Replace "*extopqisi" and "*extophisi". + ("*extop<mode>si_swap"): Replace "*extopqisi_swap" and + "*extophisi_swap". + ("<u>mul<s><mode>3"): Replace "umulhisi3", "umulqihi3", + "mulqihi3", "mulhisi3" and "mulhisi3". + ("<u>mulsidi3"): Replace "mulsidi3" and "umulsidi3". + ("<su>mulsi3_highpart"): Replace "smulsi3_highpart" and + "umulsi3_highpart". + ("xor<mode>3"): Replace "xorhi3" and "xorqi3". + ("neg<mode>2"): Replace "negsi2", "neghi2" and "negqi2". + ("one_cmpl<mode>2"): Replace "one_cmplhi2" and "one_cmplqi2". + ("<shlr>si3"): Replace "ashrsi3", "lshrsi3" and "ashlsi3". + ("ashr<mode>3"): Replace "ashrhi3" and "ashrqi3". + ("*expanded_<shlr><mode>"): Replace "*expanded_ashrhi", + "*expanded_ashrqi", "*expanded_lshrhi" and "*expanded_lshrqi". + ("*<shlr><mode>_lowpart"): Replace "*ashrhi_lowpart", + "*ashrqi_lowpart", "*lshrhi_lowpart" and "*lshrqi_lowpart". + ("lshr<mode>3"): Replace "lshrhi3" and "lshrqi3". + ("ashl<mode>3"): Replace "ashlhi3" and "ashlqi3". + ("*ashl<mode>_lowpart"): Replace "*ashlqi_lowpart" and + "*ashlhi_lowpart". + ("abs<mode>2"): Replace "abshi2" and "absqi2". + ("b<ncond>"): Replace "beq", "bne", "bgtu", "bltu", "bgeu" and + "bleu". + ("b<ocond>"): Replace "bgt" and "ble". + ("b<rcond>"): Replace "blt" and "bge". + ("*b<ncond>_reversed"): Replace "*beq_reversed", "*bne_reversed", + "*bgtu_reversed", "*bltu_reversed", "*bgeu_reversed" and + "*bleu_reversed". + ("*b<ocond>_reversed"): Replace "*bgt_reversed" and + "*ble_reversed". + ("*b<rcond>_reversed"): Replace "*blt_reversed" and + "*blt_reversed". + ("s<ncond>"): Replace "sgeu", "sltu", "seq", "sgtu", "sleu" and + "sne". + ("s<rcond>"): Replace "sge" and "slt". + ("s<ocond>"): Replace "sgt" and "sle". + ("clear.[bwd] [rx=rx+rz.S2]"): Replace split clear.d + [rx=rx+rz.S2], clear.w [rx=rx+rz.S2] and clear.b [rx=rx+rz.S2]. + ("clear.[bwd] [rx=rx+i]"): Replace splits clear.d [rx=rx+i], + clear.w [rx=rx+i] and clear.b [rx=rx+i]. + 2005-05-17 Jakub Jelinek <jakub@redhat.com> * varasm.c (struct constant_descriptor_tree): Add hash field. diff --git a/gcc/config/cris/cris.md b/gcc/config/cris/cris.md index 9e6818b..e8d330f 100644 --- a/gcc/config/cris/cris.md +++ b/gcc/config/cris/cris.md @@ -141,6 +141,46 @@ (define_delay (eq_attr "slottable" "has_slot") [(eq_attr "slottable" "yes") (nil) (nil)]) +;; Iterator definitions. + +;; For the "usual" pattern size alternatives. +(define_mode_macro BWD [SI HI QI]) +(define_mode_macro WD [SI HI]) +(define_mode_macro BW [HI QI]) +(define_mode_attr S [(SI "HI") (HI "QI")]) +(define_mode_attr s [(SI "hi") (HI "qi")]) +(define_mode_attr m [(SI ".d") (HI ".w") (QI ".b")]) +(define_mode_attr mm [(SI ".w") (HI ".b")]) +(define_mode_attr nbitsm1 [(SI "31") (HI "15") (QI "7")]) + +;; For the sign_extend+zero_extend variants. +(define_code_macro szext [sign_extend zero_extend]) +(define_code_attr u [(sign_extend "") (zero_extend "u")]) +(define_code_attr su [(sign_extend "s") (zero_extend "u")]) + +;; For the shift variants. +(define_code_macro shift [ashiftrt lshiftrt ashift]) +(define_code_macro shiftrt [ashiftrt lshiftrt]) +(define_code_attr shlr [(ashiftrt "ashr") (lshiftrt "lshr") (ashift "ashl")]) +(define_code_attr slr [(ashiftrt "asr") (lshiftrt "lsr") (ashift "lsl")]) + +;; For conditional branches and sCC. We define an attribute by the +;; same name as the macro, so the insn names here is seen as +;; b<ncond>, b<ocond> etc. rather than b<code> b<code> etc. +(define_code_macro ncond [eq ne gtu ltu geu leu]) +(define_code_attr ncond [(eq "eq") (ne "ne") (gtu "gtu") (ltu "ltu") + (geu "geu") (leu "leu")]) +(define_code_macro ocond [gt le]) +(define_code_attr ocond [(gt "gt") (le "le")]) +(define_code_macro rcond [lt ge]) +(define_code_attr rcond [(lt "lt") (ge "ge")]) +(define_code_attr CC [(eq "eq") (ne "ne") (gt "gt") (gtu "hi") (lt "lt") + (ltu "lo") (ge "ge") (geu "hs") (le "le") (leu "ls")]) +(define_code_attr rCC [(eq "ne") (ne "eq") (gt "le") (gtu "ls") (lt "ge") + (ltu "hs") (ge "lt") (geu "lo") (le "gt") (leu "hi")]) +(define_code_attr oCC [(lt "mi") (ge "pl")]) +(define_code_attr roCC [(lt "pl") (ge "mi")]) + ;; Operand and operator predicates. (include "predicates.md") @@ -165,25 +205,11 @@ ;; Normal named test patterns from SI on. ;; FIXME: Seems they should change to be in order smallest..largest. -(define_insn "tstsi" - [(set (cc0) - (match_operand:SI 0 "nonimmediate_operand" "r,Q>,m"))] - "" - "test.d %0" - [(set_attr "slottable" "yes,yes,no")]) - -(define_insn "tsthi" +(define_insn "tst<mode>" [(set (cc0) - (match_operand:HI 0 "nonimmediate_operand" "r,Q>,m"))] + (match_operand:BWD 0 "nonimmediate_operand" "r,Q>,m"))] "" - "test.w %0" - [(set_attr "slottable" "yes,yes,no")]) - -(define_insn "tstqi" - [(set (cc0) - (match_operand:QI 0 "nonimmediate_operand" "r,Q>,m"))] - "" - "test.b %0" + "test<m> %0" [(set_attr "slottable" "yes,yes,no")]) ;; It seems that the position of the sign-bit and the fact that 0.0 is @@ -233,60 +259,29 @@ ;; These are mostly useful for compares in SImode, using 8 or 16-bit ;; constants, but sometimes gcc will find its way to use it for other ;; (memory) operands. Avoid side-effect patterns, though (see above). -;; -;; FIXME: These could have an anonymous mode for operand 1. - -;; QImode - -(define_insn "*cmp_extsi" - [(set (cc0) - (compare - (match_operand:SI 0 "register_operand" "r,r") - (match_operator:SI 2 "cris_extend_operator" - [(match_operand:QI 1 "memory_operand" "Q>,m")])))] - "" - "cmp%e2.%s1 %1,%0" - [(set_attr "slottable" "yes,no")]) -;; HImode -(define_insn "*cmp_exthi" +(define_insn "*cmp_ext<mode>" [(set (cc0) (compare (match_operand:SI 0 "register_operand" "r,r") (match_operator:SI 2 "cris_extend_operator" - [(match_operand:HI 1 "memory_operand" "Q>,m")])))] + [(match_operand:BW 1 "memory_operand" "Q>,m")])))] "" - "cmp%e2.%s1 %1,%0" + "cmp%e2<m> %1,%0" [(set_attr "slottable" "yes,no")]) ;; Swap operands; it seems the canonical look (if any) is not enforced. ;; ;; FIXME: Investigate that. -;; FIXME: These could have an anonymous mode for operand 1. - -;; QImode - -(define_insn "*cmp_swapextqi" - [(set (cc0) - (compare - (match_operator:SI 2 "cris_extend_operator" - [(match_operand:QI 0 "memory_operand" "Q>,m")]) - (match_operand:SI 1 "register_operand" "r,r")))] - "" - "cmp%e2.%s0 %0,%1" ; The function cris_notice_update_cc knows about - ; swapped operands to compares. - [(set_attr "slottable" "yes,no")]) - -;; HImode -(define_insn "*cmp_swapexthi" +(define_insn "*cmp_swapext<mode>" [(set (cc0) (compare (match_operator:SI 2 "cris_extend_operator" - [(match_operand:HI 0 "memory_operand" "Q>,m")]) + [(match_operand:BW 0 "memory_operand" "Q>,m")]) (match_operand:SI 1 "register_operand" "r,r")))] "" - "cmp%e2.%s0 %0,%1" ; The function cris_notice_update_cc knows about + "cmp%e2<m> %0,%1" ; The function cris_notice_update_cc knows about ; swapped operands to compares. [(set_attr "slottable" "yes,no")]) @@ -311,37 +306,21 @@ cmp.d %0,%1" [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no")]) -(define_insn "cmphi" - [(set (cc0) - (compare (match_operand:HI 0 "nonimmediate_operand" "r,r, r,Q>,Q>,r,m,m") - (match_operand:HI 1 "general_operand" "r,Q>,M,M, r, g,M,r")))] - "" - "@ - cmp.w %1,%0 - cmp.w %1,%0 - test.w %0 - test.w %0 - cmp.w %0,%1 - cmp.w %1,%0 - test.w %0 - cmp.w %0,%1" - [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")]) - -(define_insn "cmpqi" +(define_insn "cmp<mode>" [(set (cc0) (compare - (match_operand:QI 0 "nonimmediate_operand" "r,r, r,Q>,Q>,r,m,m") - (match_operand:QI 1 "general_operand" "r,Q>,M,M, r, g,M,r")))] + (match_operand:BW 0 "nonimmediate_operand" "r,r, r,Q>,Q>,r,m,m") + (match_operand:BW 1 "general_operand" "r,Q>,M,M, r, g,M,r")))] "" "@ - cmp.b %1,%0 - cmp.b %1,%0 - test.b %0 - test.b %0 - cmp.b %0,%1 - cmp.b %1,%0 - test.b %0 - cmp.b %0,%1" + cmp<m> %1,%0 + cmp<m> %1,%0 + test<m> %0 + test<m> %0 + cmp<m> %0,%1 + cmp<m> %1,%0 + test<m> %0 + cmp<m> %0,%1" [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")]) ;; Pattern matching the BTST insn. @@ -401,11 +380,34 @@ ;; The truth has IMO is not been decided yet, so check from time to ;; time by disabling the movdi patterns. +;; To appease testcase gcc.c-torture/execute/920501-2.c (and others) at +;; -O0, we need a movdi as a temporary measure. Here's how things fail: +;; A cmpdi RTX needs reloading (global): +;; (insn 185 326 186 (set (cc0) +;; (compare (mem/f:DI (reg/v:SI 22) 0) +;; (const_int 1 [0x1]))) 4 {cmpdi} (nil) +;; (nil)) +;; Now, reg 22 is reloaded for input address, and the mem is also moved +;; out of the instruction (into a register), since one of the operands +;; must be a register. Reg 22 is reloaded (into reg 10), and the mem is +;; moved out and synthesized in SImode parts (reg 9, reg 10 - should be ok +;; wrt. overlap). The bad things happen with the synthesis in +;; emit_move_insn_1; the location where to substitute reg 10 is lost into +;; two new RTX:es, both still having reg 22. Later on, the left-over reg +;; 22 is recognized to have an equivalent in memory which is substituted +;; straight in, and we end up with an unrecognizable insn: +;; (insn 325 324 326 (set (reg:SI 9 r9) +;; (mem/f:SI (mem:SI (plus:SI (reg:SI 8 r8) +;; (const_int -84 [0xffffffac])) 0) 0)) -1 (nil) +;; (nil)) +;; which is the first part of the reloaded synthesized "movdi". +;; The right thing would be to add equivalent replacement locations for +;; insn with pseudos that need more reloading. The question is where. + (define_expand "movdi" [(set (match_operand:DI 0 "nonimmediate_operand" "") (match_operand:DI 1 "general_operand" ""))] "" - " { if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx) operands[1] = copy_to_mode_reg (DImode, operands[1]); @@ -438,7 +440,7 @@ emit_no_conflict_block (insns, op0, op1, 0, op1); DONE; } -}") +}) (define_insn "*movdi_insn" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rx,m") @@ -462,28 +464,9 @@ ;; move.S1 [rx=ry+rz.S],rw avoiding when rx is ry, or rw is rx ;; FIXME: These could have anonymous mode for operand 0. -;; QImode - -(define_insn "*mov_sideqi_biap" - [(set (match_operand:QI 0 "register_operand" "=r,r") - (mem:QI (plus:SI - (mult:SI (match_operand:SI 1 "register_operand" "r,r") - (match_operand:SI 2 "const_int_operand" "n,n")) - (match_operand:SI 3 "register_operand" "r,r")))) - (set (match_operand:SI 4 "register_operand" "=*3,r") - (plus:SI (mult:SI (match_dup 1) - (match_dup 2)) - (match_dup 3)))] - "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)" - "@ - # - move.%s0 [%4=%3+%1%T2],%0") - -;; HImode - -(define_insn "*mov_sidehi_biap" - [(set (match_operand:HI 0 "register_operand" "=r,r") - (mem:HI (plus:SI +(define_insn "*mov_side<mode>_biap" + [(set (match_operand:BW 0 "register_operand" "=r,r") + (mem:BW (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r,r") (match_operand:SI 2 "const_int_operand" "n,n")) (match_operand:SI 3 "register_operand" "r,r")))) @@ -494,9 +477,7 @@ "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)" "@ # - move.%s0 [%4=%3+%1%T2],%0") - -;; SImode + move<m> [%4=%3+%1%T2],%0") (define_insn "*mov_sidesisf_biap" [(set (match_operand 0 "register_operand" "=r,r,x,x") @@ -520,43 +501,16 @@ ;; avoiding move.S1 [ry=ry+i],rz ;; and move.S1 [rz=ry+i],rz ;; Note that "i" is allowed to be a register. -;; FIXME: These could have anonymous mode for operand 0. - -;; QImode - -(define_insn "*mov_sideqi" - [(set (match_operand:QI 0 "register_operand" "=r,r,r") - (mem:QI - (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r,r,r") - (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn")))) - (set (match_operand:SI 3 "register_operand" "=*1,r,r") - (plus:SI (match_dup 1) - (match_dup 2)))] - "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)" - "* -{ - if (which_alternative == 0 - && (GET_CODE (operands[2]) != CONST_INT - || INTVAL (operands[2]) > 127 - || INTVAL (operands[2]) < -128 - || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N') - || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))) - return \"#\"; - return \"move.%s0 [%3=%1%S2],%0\"; -}") -;; HImode - -(define_insn "*mov_sidehi" - [(set (match_operand:HI 0 "register_operand" "=r,r,r") - (mem:HI +(define_insn "*mov_side<mode>" + [(set (match_operand:BW 0 "register_operand" "=r,r,r") + (mem:BW (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r,r,r") (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn")))) (set (match_operand:SI 3 "register_operand" "=*1,r,r") (plus:SI (match_dup 1) (match_dup 2)))] "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)" - "* { if (which_alternative == 0 && (GET_CODE (operands[2]) != CONST_INT @@ -564,11 +518,9 @@ || INTVAL (operands[2]) < -128 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N') || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))) - return \"#\"; - return \"move.%s0 [%3=%1%S2],%0\"; -}") - -;; SImode + return "#"; + return "move<m> [%3=%1%S2],%0"; +}) (define_insn "*mov_sidesisf" [(set (match_operand 0 "register_operand" "=r,r,r,x,x,x") @@ -612,34 +564,13 @@ ;; ;; move.s rz,[ry=rx+rw.S] -;; FIXME: These could have anonymous mode for operand 3. - -;; QImode - -(define_insn "*mov_sideqi_biap_mem" - [(set (mem:QI (plus:SI - (mult:SI (match_operand:SI 0 "register_operand" "r,r,r") - (match_operand:SI 1 "const_int_operand" "n,n,n")) - (match_operand:SI 2 "register_operand" "r,r,r"))) - (match_operand:QI 3 "register_operand" "r,r,r")) - (set (match_operand:SI 4 "register_operand" "=*2,!3,r") - (plus:SI (mult:SI (match_dup 0) - (match_dup 1)) - (match_dup 2)))] - "cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)" - "@ - # - # - move.%s3 %3,[%4=%2+%0%T1]") - -;; HImode -(define_insn "*mov_sidehi_biap_mem" - [(set (mem:HI (plus:SI +(define_insn "*mov_side<mode>_biap_mem" + [(set (mem:BW (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "r,r,r") (match_operand:SI 1 "const_int_operand" "n,n,n")) (match_operand:SI 2 "register_operand" "r,r,r"))) - (match_operand:HI 3 "register_operand" "r,r,r")) + (match_operand:BW 3 "register_operand" "r,r,r")) (set (match_operand:SI 4 "register_operand" "=*2,!3,r") (plus:SI (mult:SI (match_dup 0) (match_dup 1)) @@ -648,9 +579,7 @@ "@ # # - move.%s3 %3,[%4=%2+%0%T1]") - -;; SImode + move<m> %3,[%4=%2+%0%T1]") (define_insn "*mov_sidesisf_biap_mem" [(set (mem (plus:SI @@ -710,16 +639,15 @@ ;; QImode -(define_insn "*mov_sideqi_mem" - [(set (mem:QI +(define_insn "*mov_side<mode>_mem" + [(set (mem:BW (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,r") (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r>Rn,r,>Rn"))) - (match_operand:QI 2 "register_operand" "r,r,r,r")) + (match_operand:BW 2 "register_operand" "r,r,r,r")) (set (match_operand:SI 3 "register_operand" "=*0,!2,r,r") (plus:SI (match_dup 0) (match_dup 1)))] "cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)" - "* { if (which_alternative == 0 && (GET_CODE (operands[1]) != CONST_INT @@ -727,36 +655,11 @@ || INTVAL (operands[1]) < -128 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N') || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J'))) - return \"#\"; - if (which_alternative == 1) - return \"#\"; - return \"move.%s2 %2,[%3=%0%S1]\"; -}") - -;; HImode - -(define_insn "*mov_sidehi_mem" - [(set (mem:HI - (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,r") - (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r>Rn,r,>Rn"))) - (match_operand:HI 2 "register_operand" "r,r,r,r")) - (set (match_operand:SI 3 "register_operand" "=*0,!2,r,r") - (plus:SI (match_dup 0) - (match_dup 1)))] - "cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)" - "* -{ - if (which_alternative == 0 - && (GET_CODE (operands[1]) != CONST_INT - || INTVAL (operands[1]) > 127 - || INTVAL (operands[1]) < -128 - || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N') - || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J'))) - return \"#\"; + return "#"; if (which_alternative == 1) - return \"#\"; - return \"move.%s2 %2,[%3=%0%S1]\"; -}") + return "#"; + return "move<m> %2,[%3=%0%S1]"; +}) ;; SImode @@ -811,53 +714,13 @@ ;; Clear memory side-effect patterns. It is hard to get to the mode if ;; the MEM was anonymous, so there will be one for each mode. -;; clear.d [ry=rx+rw.s2] - -(define_insn "*clear_sidesi_biap" - [(set (mem:SI (plus:SI - (mult:SI (match_operand:SI 0 "register_operand" "r,r") - (match_operand:SI 1 "const_int_operand" "n,n")) - (match_operand:SI 2 "register_operand" "r,r"))) - (const_int 0)) - (set (match_operand:SI 3 "register_operand" "=*2,r") - (plus:SI (mult:SI (match_dup 0) - (match_dup 1)) - (match_dup 2)))] - "cris_side_effect_mode_ok (MULT, operands, 3, 2, 0, 1, -1)" - "@ - # - clear.d [%3=%2+%0%T1]") - -;; clear.d [ry=rz+i] - -(define_insn "*clear_sidesi" - [(set (mem:SI - (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r") - (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn"))) - (const_int 0)) - (set (match_operand:SI 2 "register_operand" "=*0,r,r") - (plus:SI (match_dup 0) - (match_dup 1)))] - "cris_side_effect_mode_ok (PLUS, operands, 2, 0, 1, -1, -1)" - "* -{ - if (which_alternative == 0 - && (GET_CODE (operands[1]) != CONST_INT - || INTVAL (operands[1]) > 127 - || INTVAL (operands[1]) < -128 - || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N') - || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J'))) - return \"#\"; - return \"clear.d [%2=%0%S1]\"; -}") - -;; clear.w [ry=rx+rw.s2] +;; clear.[bwd] [ry=rx+rw.s2] -(define_insn "*clear_sidehi_biap" - [(set (mem:HI (plus:SI - (mult:SI (match_operand:SI 0 "register_operand" "r,r") - (match_operand:SI 1 "const_int_operand" "n,n")) - (match_operand:SI 2 "register_operand" "r,r"))) +(define_insn "*clear_side<mode>_biap" + [(set (mem:BWD (plus:SI + (mult:SI (match_operand:SI 0 "register_operand" "r,r") + (match_operand:SI 1 "const_int_operand" "n,n")) + (match_operand:SI 2 "register_operand" "r,r"))) (const_int 0)) (set (match_operand:SI 3 "register_operand" "=*2,r") (plus:SI (mult:SI (match_dup 0) @@ -866,12 +729,12 @@ "cris_side_effect_mode_ok (MULT, operands, 3, 2, 0, 1, -1)" "@ # - clear.w [%3=%2+%0%T1]") + clear<m> [%3=%2+%0%T1]") -;; clear.w [ry=rz+i] +;; clear.[bwd] [ry=rz+i] -(define_insn "*clear_sidehi" - [(set (mem:HI +(define_insn "*clear_side<mode>" + [(set (mem:BWD (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r") (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn"))) (const_int 0)) @@ -879,7 +742,6 @@ (plus:SI (match_dup 0) (match_dup 1)))] "cris_side_effect_mode_ok (PLUS, operands, 2, 0, 1, -1, -1)" - "* { if (which_alternative == 0 && (GET_CODE (operands[1]) != CONST_INT @@ -887,74 +749,10 @@ || INTVAL (operands[1]) < -128 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N') || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J'))) - return \"#\"; - return \"clear.w [%2=%0%S1]\"; -}") - -;; clear.b [ry=rx+rw.s2] - -(define_insn "*clear_sideqi_biap" - [(set (mem:QI (plus:SI - (mult:SI (match_operand:SI 0 "register_operand" "r,r") - (match_operand:SI 1 "const_int_operand" "n,n")) - (match_operand:SI 2 "register_operand" "r,r"))) - (const_int 0)) - (set (match_operand:SI 3 "register_operand" "=*2,r") - (plus:SI (mult:SI (match_dup 0) - (match_dup 1)) - (match_dup 2)))] - "cris_side_effect_mode_ok (MULT, operands, 3, 2, 0, 1, -1)" - "@ - # - clear.b [%3=%2+%0%T1]") - -;; clear.b [ry=rz+i] - -(define_insn "*clear_sideqi" - [(set (mem:QI - (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r") - (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn"))) - (const_int 0)) - (set (match_operand:SI 2 "register_operand" "=*0,r,r") - (plus:SI (match_dup 0) - (match_dup 1)))] - "cris_side_effect_mode_ok (PLUS, operands, 2, 0, 1, -1, -1)" - "* -{ - if (which_alternative == 0 - && (GET_CODE (operands[1]) != CONST_INT - || INTVAL (operands[1]) > 127 - || INTVAL (operands[1]) < -128 - || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N') - || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J'))) - return \"#\"; - return \"clear.b [%2=%0%S1]\"; -}") + return "#"; + return "clear<m> [%2=%0%S1]"; +}) -;; To appease testcase gcc.c-torture/execute/920501-2.c (and others) at -;; -O0, we need a movdi as a temporary measure. Here's how things fail: -;; A cmpdi RTX needs reloading (global): -;; (insn 185 326 186 (set (cc0) -;; (compare (mem/f:DI (reg/v:SI 22) 0) -;; (const_int 1 [0x1]))) 4 {cmpdi} (nil) -;; (nil)) -;; Now, reg 22 is reloaded for input address, and the mem is also moved -;; out of the instruction (into a register), since one of the operands -;; must be a register. Reg 22 is reloaded (into reg 10), and the mem is -;; moved out and synthesized in SImode parts (reg 9, reg 10 - should be ok -;; wrt. overlap). The bad things happen with the synthesis in -;; emit_move_insn_1; the location where to substitute reg 10 is lost into -;; two new RTX:es, both still having reg 22. Later on, the left-over reg -;; 22 is recognized to have an equivalent in memory which is substituted -;; straight in, and we end up with an unrecognizable insn: -;; (insn 325 324 326 (set (reg:SI 9 r9) -;; (mem/f:SI (mem:SI (plus:SI (reg:SI 8 r8) -;; (const_int -84 [0xffffffac])) 0) 0)) -1 (nil) -;; (nil)) -;; which is the first part of the reloaded synthesized "movdi". -;; The right thing would be to add equivalent replacement locations for -;; insn with pseudos that need more reloading. The question is where. - ;; Normal move patterns from SI on. (define_expand "movsi" @@ -1036,7 +834,6 @@ ;; It's a bug: an S is not a general_operand and shouldn't match g. "cris_general_operand_or_gotless_symbol" "r,Q>,M,M, I,r, M,n,!S,g,r,x, rQ>,x,gi"))] "" - "* { /* Better to have c-switch here; it is worth it to optimize the size of move insns. The alternative would be to try to find more constraint @@ -1048,38 +845,38 @@ case 5: case 9: case 10: - return \"move.d %1,%0\"; + return "move.d %1,%0"; case 11: case 12: case 13: case 14: - return \"move %d1,%0\"; + return "move %d1,%0"; case 2: case 3: case 6: - return \"clear.d %0\"; + return "clear.d %0"; /* Constants -32..31 except 0. */ case 4: - return \"moveq %1,%0\"; + return "moveq %1,%0"; /* We can win a little on constants -32768..-33, 32..65535. */ case 7: if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) < 65536) { if (INTVAL (operands[1]) < 256) - return \"movu.b %1,%0\"; - return \"movu.w %1,%0\"; + return "movu.b %1,%0"; + return "movu.w %1,%0"; } else if (INTVAL (operands[1]) >= -32768 && INTVAL (operands[1]) < 32768) { if (INTVAL (operands[1]) >= -128 && INTVAL (operands[1]) < 128) - return \"movs.b %1,%0\"; - return \"movs.w %1,%0\"; + return "movs.b %1,%0"; + return "movs.w %1,%0"; } - return \"move.d %1,%0\"; + return "move.d %1,%0"; case 8: /* FIXME: Try and split this into pieces GCC makes better code of, @@ -1103,15 +900,15 @@ CC_STATUS_INIT; CRIS_ASSERT (REGNO (operands[0]) == PIC_OFFSET_TABLE_REGNUM); - return \"move.d $pc,%0\;sub.d .:GOTOFF,%0\"; + return "move.d $pc,%0\;sub.d .:GOTOFF,%0"; } - return \"move.d %v1,%0\;add.d %P1,%0\"; + return "move.d %v1,%0\;add.d %P1,%0"; default: - return \"BOGUS: %1 to %0\"; + return "BOGUS: %1 to %0"; } -}" +} [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no,no,yes,yes,no,no") (set_attr "cc" "*,*,*,*,*,*,*,*,*,*,*,none,none,none,none")]) @@ -1142,13 +939,11 @@ # mov%e5.%m5 [%4=%3+%1%T2],%0") -;; QImode to SImode - -(define_insn "*ext_sideqisi_biap" +(define_insn "*ext_side<mode>si_biap" [(set (match_operand:SI 0 "register_operand" "=r,r") (match_operator:SI 5 "cris_extend_operator" - [(mem:QI (plus:SI + [(mem:BW (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r,r") (match_operand:SI 2 "const_int_operand" "n,n")) (match_operand:SI 3 "register_operand" "r,r")))])) @@ -1159,26 +954,7 @@ "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)" "@ # - mov%e5.%m5 [%4=%3+%1%T2],%0") - -;; HImode to SImode - -(define_insn "*ext_sidehisi_biap" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (match_operator:SI - 5 "cris_extend_operator" - [(mem:HI (plus:SI - (mult:SI (match_operand:SI 1 "register_operand" "r,r") - (match_operand:SI 2 "const_int_operand" "n,n")) - (match_operand:SI 3 "register_operand" "r,r")))])) - (set (match_operand:SI 4 "register_operand" "=*3,r") - (plus:SI (mult:SI (match_dup 1) - (match_dup 2)) - (match_dup 3)))] - "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)" - "@ - # - mov%e5.%m5 [%4=%3+%1%T2],%0") + mov%e5<m> [%4=%3+%1%T2],%0") ;; Same but [rx=ry+i] @@ -1195,32 +971,6 @@ (plus:SI (match_dup 1) (match_dup 2)))] "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)" - "* -{ - if (which_alternative == 0 - && (GET_CODE (operands[2]) != CONST_INT - || INTVAL (operands[2]) > 127 - || INTVAL (operands[2]) < -128 - || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N') - || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))) - return \"#\"; - return \"mov%e4.%m4 [%3=%1%S2],%0\"; -}") - -;; QImode to SImode - -(define_insn "*ext_sideqisi" - [(set (match_operand:SI 0 "register_operand" "=r,r,r") - (match_operator:SI - 4 "cris_extend_operator" - [(mem:QI (plus:SI - (match_operand:SI 1 "cris_bdap_operand" "%r,r,r") - (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn")))])) - (set (match_operand:SI 3 "register_operand" "=*1,r,r") - (plus:SI (match_dup 1) - (match_dup 2)))] - "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)" - "* { if (which_alternative == 0 && (GET_CODE (operands[2]) != CONST_INT @@ -1228,24 +978,21 @@ || INTVAL (operands[2]) < -128 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N') || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))) - return \"#\"; - return \"mov%e4.%m4 [%3=%1%S2],%0\"; -}") - -;; HImode to SImode + return "#"; + return "mov%e4.%m4 [%3=%1%S2],%0"; +}) -(define_insn "*ext_sidehisi" +(define_insn "*ext_side<mode>si" [(set (match_operand:SI 0 "register_operand" "=r,r,r") (match_operator:SI 4 "cris_extend_operator" - [(mem:HI (plus:SI + [(mem:BW (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r,r,r") (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn")))])) (set (match_operand:SI 3 "register_operand" "=*1,r,r") (plus:SI (match_dup 1) (match_dup 2)))] "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)" - "* { if (which_alternative == 0 && (GET_CODE (operands[2]) != CONST_INT @@ -1253,9 +1000,9 @@ || INTVAL (operands[2]) < -128 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N') || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))) - return \"#\"; - return \"mov%e4.%m4 [%3=%1%S2],%0\"; -}") + return "#"; + return "mov%e4<m> [%3=%1%S2],%0"; +}) ;; FIXME: See movsi. @@ -1264,7 +1011,6 @@ (match_operand:HI 0 "nonimmediate_operand" "=r,r, r,Q>,r,Q>,r,r,r,g,g,r,r,x") (match_operand:HI 1 "general_operand" "r,Q>,M,M, I,r, L,O,n,M,r,g,x,r"))] "" - "* { switch (which_alternative) { @@ -1273,31 +1019,31 @@ case 5: case 10: case 11: - return \"move.w %1,%0\"; + return "move.w %1,%0"; case 12: case 13: - return \"move %1,%0\"; + return "move %1,%0"; case 2: case 3: case 9: - return \"clear.w %0\"; + return "clear.w %0"; case 4: - return \"moveq %1,%0\"; + return "moveq %1,%0"; case 6: case 8: if (INTVAL (operands[1]) < 256 && INTVAL (operands[1]) >= -128) { if (INTVAL (operands[1]) > 0) - return \"movu.b %1,%0\"; - return \"movs.b %1,%0\"; + return "movu.b %1,%0"; + return "movs.b %1,%0"; } - return \"move.w %1,%0\"; + return "move.w %1,%0"; case 7: - return \"movEq %b1,%0\"; + return "movEq %b1,%0"; default: - return \"BOGUS: %1 to %0\"; + return "BOGUS: %1 to %0"; } -}" +} [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,yes,no,no,no,no,yes,yes") (set_attr "cc" "*,*,none,none,*,none,*,clobber,*,none,none,*,none,none")]) @@ -1318,18 +1064,18 @@ move.w %1,%0" [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")]) -(define_expand "reload_inhi" - [(set (match_operand:HI 2 "register_operand" "=r") - (match_operand:HI 1 "memory_operand" "m")) - (set (match_operand:HI 0 "register_operand" "=x") +(define_expand "reload_in<mode>" + [(set (match_operand:BW 2 "register_operand" "=r") + (match_operand:BW 1 "memory_operand" "m")) + (set (match_operand:BW 0 "register_operand" "=x") (match_dup 2))] "" "") -(define_expand "reload_outhi" - [(set (match_operand:HI 2 "register_operand" "=r") - (match_operand:HI 1 "register_operand" "x")) - (set (match_operand:HI 0 "memory_operand" "=m") +(define_expand "reload_out<mode>" + [(set (match_operand:BW 2 "register_operand" "=r") + (match_operand:BW 1 "register_operand" "x")) + (set (match_operand:BW 0 "memory_operand" "=m") (match_dup 2))] "" "") @@ -1370,22 +1116,6 @@ move.b %1,%0" [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")]) -(define_expand "reload_inqi" - [(set (match_operand:QI 2 "register_operand" "=r") - (match_operand:QI 1 "memory_operand" "m")) - (set (match_operand:QI 0 "register_operand" "=x") - (match_dup 2))] - "" - "") - -(define_expand "reload_outqi" - [(set (match_operand:QI 2 "register_operand" "=r") - (match_operand:QI 1 "register_operand" "x")) - (set (match_operand:QI 0 "memory_operand" "=m") - (match_dup 2))] - "" - "") - ;; The valid "quick" bit-patterns are, except for 0.0, denormalized ;; values REALLY close to 0, and some NaN:s (I think; their exponent is ;; all ones); the worthwhile one is "0.0". @@ -1452,30 +1182,17 @@ "" "move.d %1,%M0\;smi %H0\;neg.d %H0,%H0") -(define_insn "extendhidi2" +(define_insn "extend<mode>di2" [(set (match_operand:DI 0 "register_operand" "=r") - (sign_extend:DI (match_operand:HI 1 "general_operand" "g")))] + (sign_extend:DI (match_operand:BW 1 "general_operand" "g")))] "" - "movs.w %1,%M0\;smi %H0\;neg.d %H0,%H0") + "movs<m> %1,%M0\;smi %H0\;neg.d %H0,%H0") -(define_insn "extendhisi2" +(define_insn "extend<mode>si2" [(set (match_operand:SI 0 "register_operand" "=r,r,r") - (sign_extend:SI (match_operand:HI 1 "general_operand" "r,Q>,g")))] + (sign_extend:SI (match_operand:BW 1 "general_operand" "r,Q>,g")))] "" - "movs.w %1,%0" - [(set_attr "slottable" "yes,yes,no")]) - -(define_insn "extendqidi2" - [(set (match_operand:DI 0 "register_operand" "=r") - (sign_extend:DI (match_operand:QI 1 "general_operand" "g")))] - "" - "movs.b %1,%M0\;smi %H0\;neg.d %H0,%H0") - -(define_insn "extendqisi2" - [(set (match_operand:SI 0 "register_operand" "=r,r,r") - (sign_extend:SI (match_operand:QI 1 "general_operand" "r,Q>,g")))] - "" - "movs.b %1,%0" + "movs<m> %1,%0" [(set_attr "slottable" "yes,yes,no")]) ;; To do a byte->word extension, extend to dword, exept that the top half @@ -1492,20 +1209,12 @@ ;; Zero-extend. The DImode ones are synthesized by gcc, so we don't ;; specify them here. -(define_insn "zero_extendhisi2" +(define_insn "zero_extend<mode>si2" [(set (match_operand:SI 0 "register_operand" "=r,r,r") (zero_extend:SI - (match_operand:HI 1 "nonimmediate_operand" "r,Q>,m")))] + (match_operand:BW 1 "nonimmediate_operand" "r,Q>,m")))] "" - "movu.w %1,%0" - [(set_attr "slottable" "yes,yes,no")]) - -(define_insn "zero_extendqisi2" - [(set (match_operand:SI 0 "register_operand" "=r,r,r") - (zero_extend:SI - (match_operand:QI 1 "nonimmediate_operand" "r,Q>,m")))] - "" - "movu.b %1,%0" + "movu<m> %1,%0" [(set_attr "slottable" "yes,yes,no")]) ;; Same comment as sign-extend QImode to HImode above applies. @@ -1526,59 +1235,16 @@ ;; op.S [rx=ry+I],rz; (add, sub, or, and, bound). ;; ;; [rx=ry+rz.S] -;; FIXME: These could have anonymous mode for operand 0. - -;; QImode - -(define_insn "*op_sideqi_biap" - [(set (match_operand:QI 0 "register_operand" "=r,r") - (match_operator:QI - 6 "cris_orthogonal_operator" - [(match_operand:QI 1 "register_operand" "0,0") - (mem:QI (plus:SI - (mult:SI (match_operand:SI 2 "register_operand" "r,r") - (match_operand:SI 3 "const_int_operand" "n,n")) - (match_operand:SI 4 "register_operand" "r,r")))])) - (set (match_operand:SI 5 "register_operand" "=*4,r") - (plus:SI (mult:SI (match_dup 2) - (match_dup 3)) - (match_dup 4)))] - "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" - "@ - # - %x6.%s0 [%5=%4+%2%T3],%0") - -;; HImode -(define_insn "*op_sidehi_biap" - [(set (match_operand:HI 0 "register_operand" "=r,r") - (match_operator:HI - 6 "cris_orthogonal_operator" - [(match_operand:HI 1 "register_operand" "0,0") - (mem:HI (plus:SI - (mult:SI (match_operand:SI 2 "register_operand" "r,r") - (match_operand:SI 3 "const_int_operand" "n,n")) - (match_operand:SI 4 "register_operand" "r,r")))])) - (set (match_operand:SI 5 "register_operand" "=*4,r") - (plus:SI (mult:SI (match_dup 2) - (match_dup 3)) - (match_dup 4)))] - "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" - "@ - # - %x6.%s0 [%5=%4+%2%T3],%0") - -;; SImode - -(define_insn "*op_sidesi_biap" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (match_operator:SI +(define_insn "*op_side<mode>_biap" + [(set (match_operand:BWD 0 "register_operand" "=r,r") + (match_operator:BWD 6 "cris_orthogonal_operator" - [(match_operand:SI 1 "register_operand" "0,0") - (mem:SI (plus:SI - (mult:SI (match_operand:SI 2 "register_operand" "r,r") - (match_operand:SI 3 "const_int_operand" "n,n")) - (match_operand:SI 4 "register_operand" "r,r")))])) + [(match_operand:BWD 1 "register_operand" "0,0") + (mem:BWD (plus:SI + (mult:SI (match_operand:SI 2 "register_operand" "r,r") + (match_operand:SI 3 "const_int_operand" "n,n")) + (match_operand:SI 4 "register_operand" "r,r")))])) (set (match_operand:SI 5 "register_operand" "=*4,r") (plus:SI (mult:SI (match_dup 2) (match_dup 3)) @@ -1586,52 +1252,22 @@ "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" "@ # - %x6.%s0 [%5=%4+%2%T3],%0") + %x6<m> [%5=%4+%2%T3],%0") ;; [rx=ry+i] ([%4=%2+%3]) -;; FIXME: These could have anonymous mode for operand 0. - -;; QImode - -(define_insn "*op_sideqi" - [(set (match_operand:QI 0 "register_operand" "=r,r,r") - (match_operator:QI - 5 "cris_orthogonal_operator" - [(match_operand:QI 1 "register_operand" "0,0,0") - (mem:QI (plus:SI - (match_operand:SI 2 "cris_bdap_operand" "%r,r,r") - (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))])) - (set (match_operand:SI 4 "register_operand" "=*2,r,r") - (plus:SI (match_dup 2) - (match_dup 3)))] - "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" - "* -{ - if (which_alternative == 0 - && (GET_CODE (operands[3]) != CONST_INT - || INTVAL (operands[3]) > 127 - || INTVAL (operands[3]) < -128 - || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N') - || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J'))) - return \"#\"; - return \"%x5.%s0 [%4=%2%S3],%0\"; -}") - -;; HImode -(define_insn "*op_sidehi" - [(set (match_operand:HI 0 "register_operand" "=r,r,r") - (match_operator:HI +(define_insn "*op_side<mode>" + [(set (match_operand:BWD 0 "register_operand" "=r,r,r") + (match_operator:BWD 5 "cris_orthogonal_operator" - [(match_operand:HI 1 "register_operand" "0,0,0") - (mem:HI (plus:SI + [(match_operand:BWD 1 "register_operand" "0,0,0") + (mem:BWD (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r") (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))])) (set (match_operand:SI 4 "register_operand" "=*2,r,r") (plus:SI (match_dup 2) (match_dup 3)))] "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" - "* { if (which_alternative == 0 && (GET_CODE (operands[3]) != CONST_INT @@ -1639,35 +1275,9 @@ || INTVAL (operands[3]) < -128 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N') || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J'))) - return \"#\"; - return \"%x5.%s0 [%4=%2%S3],%0\"; -}") - -;; SImode - -(define_insn "*op_sidesi" - [(set (match_operand:SI 0 "register_operand" "=r,r,r") - (match_operator:SI - 5 "cris_orthogonal_operator" - [(match_operand:SI 1 "register_operand" "0,0,0") - (mem:SI (plus:SI - (match_operand:SI 2 "cris_bdap_operand" "%r,r,r") - (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))])) - (set (match_operand:SI 4 "register_operand" "=*2,r,r") - (plus:SI (match_dup 2) - (match_dup 3)))] - "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" - "* -{ - if (which_alternative == 0 - && (GET_CODE (operands[3]) != CONST_INT - || INTVAL (operands[3]) > 127 - || INTVAL (operands[3]) < -128 - || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N') - || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J'))) - return \"#\"; - return \"%x5.%s0 [%4=%2%S3],%0\"; -}") + return "#"; + return "%x5<m> [%4=%2%S3],%0"; +}) ;; To match all cases for commutative operations we may have to have the ;; following pattern for add, or & and. I do not know really, but it does @@ -1678,59 +1288,16 @@ ;; op.S [rx=ry+I],rz; ;; ;; [rx=ry+rz.S] -;; FIXME: These could have anonymous mode for operand 0. - -;; QImode - -(define_insn "*op_swap_sideqi_biap" - [(set (match_operand:QI 0 "register_operand" "=r,r") - (match_operator:QI - 6 "cris_commutative_orth_op" - [(mem:QI (plus:SI - (mult:SI (match_operand:SI 2 "register_operand" "r,r") - (match_operand:SI 3 "const_int_operand" "n,n")) - (match_operand:SI 4 "register_operand" "r,r"))) - (match_operand:QI 1 "register_operand" "0,0")])) - (set (match_operand:SI 5 "register_operand" "=*4,r") - (plus:SI (mult:SI (match_dup 2) - (match_dup 3)) - (match_dup 4)))] - "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" - "@ - # - %x6.%s0 [%5=%4+%2%T3],%0") - -;; HImode - -(define_insn "*op_swap_sidehi_biap" - [(set (match_operand:HI 0 "register_operand" "=r,r") - (match_operator:HI - 6 "cris_commutative_orth_op" - [(mem:HI (plus:SI - (mult:SI (match_operand:SI 2 "register_operand" "r,r") - (match_operand:SI 3 "const_int_operand" "n,n")) - (match_operand:SI 4 "register_operand" "r,r"))) - (match_operand:HI 1 "register_operand" "0,0")])) - (set (match_operand:SI 5 "register_operand" "=*4,r") - (plus:SI (mult:SI (match_dup 2) - (match_dup 3)) - (match_dup 4)))] - "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" - "@ - # - %x6.%s0 [%5=%4+%2%T3],%0") -;; SImode - -(define_insn "*op_swap_sidesi_biap" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (match_operator:SI +(define_insn "*op_swap_side<mode>_biap" + [(set (match_operand:BWD 0 "register_operand" "=r,r") + (match_operator:BWD 6 "cris_commutative_orth_op" - [(mem:SI (plus:SI + [(mem:BWD (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r,r") (match_operand:SI 3 "const_int_operand" "n,n")) (match_operand:SI 4 "register_operand" "r,r"))) - (match_operand:SI 1 "register_operand" "0,0")])) + (match_operand:BWD 1 "register_operand" "0,0")])) (set (match_operand:SI 5 "register_operand" "=*4,r") (plus:SI (mult:SI (match_dup 2) (match_dup 3)) @@ -1738,26 +1305,25 @@ "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" "@ # - %x6.%s0 [%5=%4+%2%T3],%0") + %x6<m> [%5=%4+%2%T3],%0") ;; [rx=ry+i] ([%4=%2+%3]) ;; FIXME: These could have anonymous mode for operand 0. ;; QImode -(define_insn "*op_swap_sideqi" - [(set (match_operand:QI 0 "register_operand" "=r,r,r") - (match_operator:QI +(define_insn "*op_swap_side<mode>" + [(set (match_operand:BWD 0 "register_operand" "=r,r,r") + (match_operator:BWD 5 "cris_commutative_orth_op" - [(mem:QI + [(mem:BWD (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r") (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn"))) - (match_operand:QI 1 "register_operand" "0,0,0")])) + (match_operand:BWD 1 "register_operand" "0,0,0")])) (set (match_operand:SI 4 "register_operand" "=*2,r,r") (plus:SI (match_dup 2) (match_dup 3)))] "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" - "* { if (which_alternative == 0 && (GET_CODE (operands[3]) != CONST_INT @@ -1765,61 +1331,9 @@ || INTVAL (operands[3]) < -128 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N') || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J'))) - return \"#\"; - return \"%x5.%s0 [%4=%2%S3],%0\"; -}") - -;; HImode - -(define_insn "*op_swap_sidehi" - [(set (match_operand:HI 0 "register_operand" "=r,r,r") - (match_operator:HI - 5 "cris_commutative_orth_op" - [(mem:HI - (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r") - (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn"))) - (match_operand:HI 1 "register_operand" "0,0,0")])) - (set (match_operand:SI 4 "register_operand" "=*2,r,r") - (plus:SI (match_dup 2) - (match_dup 3)))] - "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" - "* -{ - if (which_alternative == 0 - && (GET_CODE (operands[3]) != CONST_INT - || INTVAL (operands[3]) > 127 - || INTVAL (operands[3]) < -128 - || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N') - || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J'))) - return \"#\"; - return \"%x5.%s0 [%4=%2%S3],%0\"; -}") - -;; SImode - -(define_insn "*op_swap_sidesi" - [(set (match_operand:SI 0 "register_operand" "=r,r,r") - (match_operator:SI - 5 "cris_commutative_orth_op" - [(mem:SI - (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r") - (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn"))) - (match_operand:SI 1 "register_operand" "0,0,0")])) - (set (match_operand:SI 4 "register_operand" "=*2,r,r") - (plus:SI (match_dup 2) - (match_dup 3)))] - "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" - "* -{ - if (which_alternative == 0 - && (GET_CODE (operands[3]) != CONST_INT - || INTVAL (operands[3]) > 127 - || INTVAL (operands[3]) < -128 - || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N') - || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J'))) - return \"#\"; - return \"%x5.%s0 [%4=%2%S3],%0\"; -}") + return "#"; + return "%x5<m> [%4=%2%S3],%0"; +}) ;; Add operations, standard names. @@ -1850,45 +1364,44 @@ ;; gcc <= 2.7.2. FIXME: Check for gcc-2.9x "" - "* { switch (which_alternative) { case 0: case 1: - return \"add.d %2,%0\"; + return "add.d %2,%0"; case 2: - return \"addq %2,%0\"; + return "addq %2,%0"; case 3: - return \"subq %n2,%0\"; + return "subq %n2,%0"; case 4: /* 'Known value', but not in -63..63. Check if addu/subu may be used. */ if (INTVAL (operands[2]) > 0) { if (INTVAL (operands[2]) < 256) - return \"addu.b %2,%0\"; + return "addu.b %2,%0"; if (INTVAL (operands[2]) < 65536) - return \"addu.w %2,%0\"; + return "addu.w %2,%0"; } else { if (INTVAL (operands[2]) >= -255) - return \"subu.b %n2,%0\"; + return "subu.b %n2,%0"; if (INTVAL (operands[2]) >= -65535) - return \"subu.w %n2,%0\"; + return "subu.w %n2,%0"; } - return \"add.d %2,%0\"; + return "add.d %2,%0"; case 6: - return \"add.d %2,%1,%0\"; + return "add.d %2,%1,%0"; case 5: - return \"add.d %2,%0\"; + return "add.d %2,%0"; case 7: - return \"add.d %1,%0\"; + return "add.d %1,%0"; default: - return \"BOGUS addsi %2+%1 to %0\"; + return "BOGUS addsi %2+%1 to %0"; } -}" +} [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,yes")]) (define_insn "addhi3" @@ -1963,33 +1476,18 @@ sub.d %2,%1,%0" [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no")]) -(define_insn "subhi3" - [(set (match_operand:HI 0 "register_operand" "=r,r, r,r,r,r") - (minus:HI (match_operand:HI 1 "register_operand" "0,0, 0,0,0,r") - (match_operand:HI 2 "general_operand" "r,Q>,J,N,g,!To")))] +(define_insn "sub<mode>3" + [(set (match_operand:BW 0 "register_operand" "=r,r, r,r,r,r") + (minus:BW (match_operand:BW 1 "register_operand" "0,0, 0,0,0,r") + (match_operand:BW 2 "general_operand" "r,Q>,J,N,g,!To")))] "" "@ - sub.w %2,%0 - sub.w %2,%0 + sub<m> %2,%0 + sub<m> %2,%0 subq %2,%0 addq %n2,%0 - sub.w %2,%0 - sub.w %2,%1,%0" - [(set_attr "slottable" "yes,yes,yes,yes,no,no") - (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")]) - -(define_insn "subqi3" - [(set (match_operand:QI 0 "register_operand" "=r,r, r,r,r,r") - (minus:QI (match_operand:QI 1 "register_operand" "0,0, 0,0,0,r") - (match_operand:QI 2 "general_operand" "r,Q>,J,N,g,!To")))] - "" - "@ - sub.b %2,%0 - sub.b %2,%0 - subq %2,%0 - addq %2,%0 - sub.b %2,%0 - sub.b %2,%1,%0" + sub<m> %2,%0 + sub<m> %2,%1,%0" [(set_attr "slottable" "yes,yes,yes,yes,no,no") (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")]) @@ -2005,7 +1503,6 @@ ;; ADDS/SUBS/ADDU/SUBU and BOUND, which needs a check for zero_extend ;; ;; adds/subs/addu/subu bound [rx=ry+rz.S] -;; FIXME: These could have anonymous mode for operand 0. ;; QImode to HImode ;; FIXME: GCC should widen. @@ -2030,16 +1527,14 @@ # %x6%e7.%m7 [%5=%4+%2%T3],%0") -;; QImode to SImode - -(define_insn "*extopqisi_side_biap" +(define_insn "*extop<mode>si_side_biap" [(set (match_operand:SI 0 "register_operand" "=r,r") (match_operator:SI 6 "cris_operand_extend_operator" [(match_operand:SI 1 "register_operand" "0,0") (match_operator:SI 7 "cris_extend_operator" - [(mem:QI (plus:SI + [(mem:BW (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r,r") (match_operand:SI 3 "const_int_operand" "n,n")) (match_operand:SI 4 "register_operand" "r,r")))])])) @@ -2051,34 +1546,10 @@ && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" "@ # - %x6%e7.%m7 [%5=%4+%2%T3],%0") - -;; HImode to SImode - -(define_insn "*extophisi_side_biap" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (match_operator:SI - 6 "cris_operand_extend_operator" - [(match_operand:SI 1 "register_operand" "0,0") - (match_operator:SI - 7 "cris_extend_operator" - [(mem:HI (plus:SI - (mult:SI (match_operand:SI 2 "register_operand" "r,r") - (match_operand:SI 3 "const_int_operand" "n,n")) - (match_operand:SI 4 "register_operand" "r,r")))])])) - (set (match_operand:SI 5 "register_operand" "=*4,r") - (plus:SI (mult:SI (match_dup 2) - (match_dup 3)) - (match_dup 4)))] - "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[7]) == ZERO_EXTEND) - && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" - "@ - # - %x6%e7.%m7 [%5=%4+%2%T3],%0") + %x6%e7<m> [%5=%4+%2%T3],%0") ;; [rx=ry+i] -;; FIXME: These could have anonymous mode for operand 0. ;; QImode to HImode @@ -2097,38 +1568,6 @@ (plus:SI (match_dup 2) (match_dup 3)))] "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" - "* -{ - if (which_alternative == 0 - && (GET_CODE (operands[3]) != CONST_INT - || INTVAL (operands[3]) > 127 - || INTVAL (operands[3]) < -128 - || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N') - || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J'))) - return \"#\"; - return \"%x5%e6.%m6 [%4=%2%S3],%0\"; -}") - -;; QImode to SImode - -(define_insn "*extopqisi_side" - [(set (match_operand:SI 0 "register_operand" "=r,r,r") - (match_operator:SI - 5 "cris_operand_extend_operator" - [(match_operand:SI 1 "register_operand" "0,0,0") - (match_operator:SI - 6 "cris_extend_operator" - [(mem:QI - (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r") - (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn") - ))])])) - (set (match_operand:SI 4 "register_operand" "=*2,r,r") - (plus:SI (match_dup 2) - (match_dup 3)))] - - "(GET_CODE (operands[5]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND) - && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" - "* { if (which_alternative == 0 && (GET_CODE (operands[3]) != CONST_INT @@ -2136,20 +1575,18 @@ || INTVAL (operands[3]) < -128 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N') || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J'))) - return \"#\"; - return \"%x5%e6.%m6 [%4=%2%S3],%0\"; -}") - -;; HImode to SImode + return "#"; + return "%x5%e6.%m6 [%4=%2%S3],%0"; +}) -(define_insn "*extophisi_side" +(define_insn "*extop<mode>si_side" [(set (match_operand:SI 0 "register_operand" "=r,r,r") (match_operator:SI 5 "cris_operand_extend_operator" [(match_operand:SI 1 "register_operand" "0,0,0") (match_operator:SI 6 "cris_extend_operator" - [(mem:HI + [(mem:BW (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r") (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn") ))])])) @@ -2158,7 +1595,6 @@ (match_dup 3)))] "(GET_CODE (operands[5]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND) && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" - "* { if (which_alternative == 0 && (GET_CODE (operands[3]) != CONST_INT @@ -2166,9 +1602,9 @@ || INTVAL (operands[3]) < -128 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N') || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J'))) - return \"#\"; - return \"%x5%e6.%m6 [%4=%2%S3],%0\"; -}") + return "#"; + return "%x5%e6<m> [%4=%2%S3],%0"; +}) ;; As with op.S we may have to add special pattern to match commuted @@ -2198,37 +1634,13 @@ # add%e6.b [%5=%4+%2%T3],%0") -;; QImode to SImode - -(define_insn "*extopqisi_swap_side_biap" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (match_operator:SI - 7 "cris_plus_or_bound_operator" - [(match_operator:SI - 6 "cris_extend_operator" - [(mem:QI (plus:SI - (mult:SI (match_operand:SI 2 "register_operand" "r,r") - (match_operand:SI 3 "const_int_operand" "n,n")) - (match_operand:SI 4 "register_operand" "r,r")))]) - (match_operand:SI 1 "register_operand" "0,0")])) - (set (match_operand:SI 5 "register_operand" "=*4,r") - (plus:SI (mult:SI (match_dup 2) - (match_dup 3)) - (match_dup 4)))] - "(GET_CODE (operands[7]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND) - && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" - "@ - # - %x7%e6.%m6 [%5=%4+%2%T3],%0") - -;; HImode to SImode -(define_insn "*extophisi_swap_side_biap" +(define_insn "*extop<mode>si_swap_side_biap" [(set (match_operand:SI 0 "register_operand" "=r,r") (match_operator:SI 7 "cris_plus_or_bound_operator" [(match_operator:SI 6 "cris_extend_operator" - [(mem:HI (plus:SI + [(mem:BW (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r,r") (match_operand:SI 3 "const_int_operand" "n,n")) (match_operand:SI 4 "register_operand" "r,r")))]) @@ -2241,10 +1653,9 @@ && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)" "@ # - %x7%e6.%m6 [%5=%4+%2%T3],%0") + %x7%e6<m> [%5=%4+%2%T3],%0") ;; [rx=ry+i] -;; FIXME: These could have anonymous mode for operand 0. ;; FIXME: GCC should widen. ;; QImode to HImode @@ -2262,36 +1673,6 @@ (plus:SI (match_dup 2) (match_dup 3)))] "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" - "* -{ - if (which_alternative == 0 - && (GET_CODE (operands[3]) != CONST_INT - || INTVAL (operands[3]) > 127 - || INTVAL (operands[3]) < -128 - || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N') - || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J'))) - return \"#\"; - return \"add%e5.b [%4=%2%S3],%0\"; -}") - -;; QImode to SImode - -(define_insn "*extopqisi_swap_side" - [(set (match_operand:SI 0 "register_operand" "=r,r,r") - (match_operator:SI - 6 "cris_plus_or_bound_operator" - [(match_operator:SI - 5 "cris_extend_operator" - [(mem:QI (plus:SI - (match_operand:SI 2 "cris_bdap_operand" "%r,r,r") - (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))]) - (match_operand:SI 1 "register_operand" "0,0,0")])) - (set (match_operand:SI 4 "register_operand" "=*2,r,r") - (plus:SI (match_dup 2) - (match_dup 3)))] - "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[5]) == ZERO_EXTEND) - && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" - "* { if (which_alternative == 0 && (GET_CODE (operands[3]) != CONST_INT @@ -2299,19 +1680,17 @@ || INTVAL (operands[3]) < -128 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N') || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J'))) - return \"#\"; - return \"%x6%e5.%m5 [%4=%2%S3],%0\"; -}") - -;; HImode to SImode + return "#"; + return "add%e5.b [%4=%2%S3],%0"; +}) -(define_insn "*extophisi_swap_side" +(define_insn "*extop<mode>si_swap_side" [(set (match_operand:SI 0 "register_operand" "=r,r,r") (match_operator:SI 6 "cris_plus_or_bound_operator" [(match_operator:SI 5 "cris_extend_operator" - [(mem:HI (plus:SI + [(mem:BW (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r") (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn")))]) (match_operand:SI 1 "register_operand" "0,0,0")])) @@ -2320,7 +1699,6 @@ (match_dup 3)))] "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[5]) == ZERO_EXTEND) && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)" - "* { if (which_alternative == 0 && (GET_CODE (operands[3]) != CONST_INT @@ -2328,12 +1706,11 @@ || INTVAL (operands[3]) < -128 || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N') || CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J'))) - return \"#\"; - return \"%x6%e5.%m5 [%4=%2%S3],%0\"; -}") + return "#"; + return "%x6%e5<m> [%4=%2%S3],%0"; +}) ;; Extend versions (zero/sign) of normal add/sub (no side-effects). -;; FIXME: These could have anonymous mode for operand 0. ;; QImode to HImode ;; FIXME: GCC should widen. @@ -2358,42 +1735,22 @@ ;; QImode to SImode -(define_insn "*extopqisi" - [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") - (match_operator:SI - 3 "cris_operand_extend_operator" - [(match_operand:SI 1 "register_operand" "0,0,0,r") - (match_operator:SI - 4 "cris_extend_operator" - [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])]))] - "(GET_CODE (operands[3]) != UMIN || GET_CODE (operands[4]) == ZERO_EXTEND) - && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD - && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)" - "@ - %x3%e4.%m4 %2,%0 - %x3%e4.%m4 %2,%0 - %x3%e4.%m4 %2,%0 - %x3%e4.%m4 %2,%1,%0" - [(set_attr "slottable" "yes,yes,no,no")]) - -;; HImode to SImode - -(define_insn "*extophisi" +(define_insn "*extop<mode>si" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") (match_operator:SI 3 "cris_operand_extend_operator" [(match_operand:SI 1 "register_operand" "0,0,0,r") (match_operator:SI 4 "cris_extend_operator" - [(match_operand:HI 2 "nonimmediate_operand" "r,Q>,m,!To")])]))] + [(match_operand:BW 2 "nonimmediate_operand" "r,Q>,m,!To")])]))] "(GET_CODE (operands[3]) != UMIN || GET_CODE (operands[4]) == ZERO_EXTEND) && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)" "@ - %x3%e4.%m4 %2,%0 - %x3%e4.%m4 %2,%0 - %x3%e4.%m4 %2,%0 - %x3%e4.%m4 %2,%1,%0" + %x3%e4<m> %2,%0 + %x3%e4<m> %2,%0 + %x3%e4<m> %2,%0 + %x3%e4<m> %2,%1,%0" [(set_attr "slottable" "yes,yes,no,no")]) @@ -2418,42 +1775,21 @@ [(set_attr "slottable" "yes,yes,no,no") (set_attr "cc" "clobber")]) -;; QImode to SImode - -(define_insn "*extopqisi_swap" +(define_insn "*extop<mode>si_swap" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") (match_operator:SI 4 "cris_plus_or_bound_operator" [(match_operator:SI 3 "cris_extend_operator" - [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")]) + [(match_operand:BW 2 "nonimmediate_operand" "r,Q>,m,!To")]) (match_operand:SI 1 "register_operand" "0,0,0,r")]))] "(GET_CODE (operands[4]) != UMIN || GET_CODE (operands[3]) == ZERO_EXTEND) && operands[1] != frame_pointer_rtx" "@ - %x4%e3.%m3 %2,%0 - %x4%e3.%m3 %2,%0 - %x4%e3.%m3 %2,%0 - %x4%e3.%m3 %2,%1,%0" - [(set_attr "slottable" "yes,yes,no,no")]) - -;; HImode to SImode - -(define_insn "*extophisi_swap" - [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") - (match_operator:SI - 4 "cris_plus_or_bound_operator" - [(match_operator:SI - 3 "cris_extend_operator" - [(match_operand:HI 2 "nonimmediate_operand" "r,Q>,m,!To")]) - (match_operand:SI 1 "register_operand" "0,0,0,r")]))] - "(GET_CODE (operands[4]) != UMIN || GET_CODE (operands[3]) == ZERO_EXTEND) - && operands[1] != frame_pointer_rtx" - "@ - %x4%e3.%m3 %2,%0 - %x4%e3.%m3 %2,%0 - %x4%e3.%m3 %2,%0 - %x4%e3.%m3 %2,%1,%0" + %x4%e3<m> %2,%0 + %x4%e3<m> %2,%0 + %x4%e3<m> %2,%0 + %x4%e3<m> %2,%1,%0" [(set_attr "slottable" "yes,yes,no,no")]) ;; This is the special case when we use what corresponds to the @@ -2514,18 +1850,17 @@ && (INTVAL (operands[2]) == 2 || INTVAL (operands[2]) == 4 || INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 5)" - "* { if (INTVAL (operands[2]) == 2) - return \"lslq 1,%0\"; + return "lslq 1,%0"; else if (INTVAL (operands[2]) == 4) - return \"lslq 2,%0\"; + return "lslq 2,%0"; else if (INTVAL (operands[2]) == 3) - return \"addi %0.w,%0\"; + return "addi %0.w,%0"; else if (INTVAL (operands[2]) == 5) - return \"addi %0.d,%0\"; - return \"BAD: adr_mulsi: %0=%1*%2\"; -}" + return "addi %0.d,%0"; + return "BAD: adr_mulsi: %0=%1*%2"; +} [(set_attr "slottable" "yes") ;; No flags are changed if this insn is "addi", but it does not seem ;; worth the trouble to distinguish that to the lslq cases. @@ -2586,34 +1921,22 @@ "mstep %2,%0" [(set_attr "slottable" "yes")]) -(define_insn "umulhisi3" - [(set (match_operand:SI 0 "register_operand" "=r") - (mult:SI - (zero_extend:SI (match_operand:HI 1 "register_operand" "%0")) - (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))) +(define_insn "<u>mul<s><mode>3" + [(set (match_operand:WD 0 "register_operand" "=r") + (mult:WD + (szext:WD (match_operand:<S> 1 "register_operand" "%0")) + (szext:WD (match_operand:<S> 2 "register_operand" "r")))) (clobber (match_scratch:SI 3 "=h"))] "TARGET_HAS_MUL_INSNS" - "%!mulu.w %2,%0" + "%!mul<su><mm> %2,%0" [(set (attr "slottable") (if_then_else (ne (symbol_ref "TARGET_MUL_BUG") (const_int 0)) (const_string "no") (const_string "yes"))) - ;; Just N unusable here, but let's be safe. - (set_attr "cc" "clobber")]) - -(define_insn "umulqihi3" - [(set (match_operand:HI 0 "register_operand" "=r") - (mult:HI - (zero_extend:HI (match_operand:QI 1 "register_operand" "%0")) - (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))) - (clobber (match_scratch:SI 3 "=h"))] - "TARGET_HAS_MUL_INSNS" - "%!mulu.b %2,%0" - [(set (attr "slottable") - (if_then_else (ne (symbol_ref "TARGET_MUL_BUG") (const_int 0)) - (const_string "no") - (const_string "yes"))) - ;; Not exactly sure, but let's be safe. + ;; For umuls.[bwd] it's just N unusable here, but let's be safe. + ;; For muls.b, this really extends to SImode, so cc should be + ;; considered clobbered. + ;; For muls.w, it's just N unusable here, but let's be safe. (set_attr "cc" "clobber")]) ;; Note that gcc does not make use of such a thing as umulqisi3. It gets @@ -2638,60 +1961,20 @@ ;; A few multiply variations. -;; This really extends to SImode, so cc should be considered clobbered. - -(define_insn "mulqihi3" - [(set (match_operand:HI 0 "register_operand" "=r") - (mult:HI - (sign_extend:HI (match_operand:QI 1 "register_operand" "%0")) - (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))) - (clobber (match_scratch:SI 3 "=h"))] - "TARGET_HAS_MUL_INSNS" - "%!muls.b %2,%0" - [(set (attr "slottable") - (if_then_else (ne (symbol_ref "TARGET_MUL_BUG") (const_int 0)) - (const_string "no") - (const_string "yes"))) - (set_attr "cc" "clobber")]) - -(define_insn "mulhisi3" - [(set (match_operand:SI 0 "register_operand" "=r") - (mult:SI - (sign_extend:SI (match_operand:HI 1 "register_operand" "%0")) - (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))) - (clobber (match_scratch:SI 3 "=h"))] - "TARGET_HAS_MUL_INSNS" - "%!muls.w %2,%0" - [(set (attr "slottable") - (if_then_else (ne (symbol_ref "TARGET_MUL_BUG") (const_int 0)) - (const_string "no") - (const_string "yes"))) - ;; Just N unusable here, but let's be safe. - (set_attr "cc" "clobber")]) - ;; When needed, we can get the high 32 bits from the overflow ;; register. We don't care to split and optimize these. ;; ;; Note that cc0 is still valid after the move-from-overflow-register ;; insn; no special precaution need to be taken in cris_notice_update_cc. -(define_insn "mulsidi3" +(define_insn "<u>mulsidi3" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI - (sign_extend:DI (match_operand:SI 1 "register_operand" "%0")) - (sign_extend:DI (match_operand:SI 2 "register_operand" "r")))) + (szext:DI (match_operand:SI 1 "register_operand" "%0")) + (szext:DI (match_operand:SI 2 "register_operand" "r")))) (clobber (match_scratch:SI 3 "=h"))] "TARGET_HAS_MUL_INSNS" - "%!muls.d %2,%M0\;move $mof,%H0") - -(define_insn "umulsidi3" - [(set (match_operand:DI 0 "register_operand" "=r") - (mult:DI - (zero_extend:DI (match_operand:SI 1 "register_operand" "%0")) - (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))) - (clobber (match_scratch:SI 3 "=h"))] - "TARGET_HAS_MUL_INSNS" - "%!mulu.d %2,%M0\;move $mof,%H0") + "%!mul<su>.d %2,%M0\;move $mof,%H0") ;; These two patterns may be expressible by other means, perhaps by making ;; [u]?mulsidi3 a define_expand. @@ -2707,39 +1990,21 @@ ;; punished by force of one "?". Check code from "int d (int a) {return ;; a / 1000;}" and unsigned. FIXME: Comment above was for 3.2, revisit. -(define_insn "smulsi3_highpart" +(define_insn "<su>mulsi3_highpart" [(set (match_operand:SI 0 "nonimmediate_operand" "=h,h,?r,?r") (truncate:SI (lshiftrt:DI (mult:DI - (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r,0,r")) - (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r,r,0"))) - (const_int 32)))) - (clobber (match_scratch:SI 3 "=1,2,h,h"))] - "TARGET_HAS_MUL_INSNS" - "@ - %!muls.d %2,%1 - %!muls.d %1,%2 - %!muls.d %2,%1\;move $mof,%0 - %!muls.d %1,%2\;move $mof,%0" - [(set_attr "slottable" "yes,yes,no,no") - (set_attr "cc" "clobber")]) - -(define_insn "umulsi3_highpart" - [(set (match_operand:SI 0 "register_operand" "=h,h,?r,?r") - (truncate:SI - (lshiftrt:DI - (mult:DI - (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r,0,r")) - (zero_extend:DI (match_operand:SI 2 "register_operand" "r,r,r,0"))) + (szext:DI (match_operand:SI 1 "register_operand" "r,r,0,r")) + (szext:DI (match_operand:SI 2 "register_operand" "r,r,r,0"))) (const_int 32)))) (clobber (match_scratch:SI 3 "=1,2,h,h"))] "TARGET_HAS_MUL_INSNS" "@ - %!mulu.d %2,%1 - %!mulu.d %1,%2 - %!mulu.d %2,%1\;move $mof,%0 - %!mulu.d %1,%2\;move $mof,%0" + %!mul<su>.d %2,%1 + %!mul<su>.d %1,%2 + %!mul<su>.d %2,%1\;move $mof,%0 + %!mul<su>.d %1,%2\;move $mof,%0" [(set_attr "slottable" "yes,yes,no,no") (set_attr "cc" "clobber")]) @@ -2802,7 +2067,6 @@ (and:SI (match_operand:SI 1 "nonimmediate_operand" "") (match_operand:SI 2 "general_operand" "")))] "" - " { if (! (GET_CODE (operands[2]) == CONST_INT && (((INTVAL (operands[2]) == -256 @@ -2839,7 +2103,7 @@ DONE; } -}") +}) ;; Some special cases of andsi3. @@ -2901,7 +2165,6 @@ (and:HI (match_operand:HI 1 "nonimmediate_operand" "") (match_operand:HI 2 "general_operand" "")))] "" - " { if (! (GET_CODE (operands[2]) == CONST_INT && (((INTVAL (operands[2]) == -256 @@ -2929,7 +2192,7 @@ DONE; } -}") +}) ;; Some fast andhi3 special cases. @@ -3078,6 +2341,7 @@ ;; Exclusive-or ;; See comment about "anddi3" for xordi3 - no need for such a pattern. +;; FIXME: Do we really need the shorter variants? (define_insn "xorsi3" [(set (match_operand:SI 0 "register_operand" "=r") @@ -3087,19 +2351,10 @@ "xor %2,%0" [(set_attr "slottable" "yes")]) -(define_insn "xorhi3" - [(set (match_operand:HI 0 "register_operand" "=r") - (xor:HI (match_operand:HI 1 "register_operand" "%0") - (match_operand:HI 2 "register_operand" "r")))] - "" - "xor %2,%0" - [(set_attr "slottable" "yes") - (set_attr "cc" "clobber")]) - -(define_insn "xorqi3" - [(set (match_operand:QI 0 "register_operand" "=r") - (xor:QI (match_operand:QI 1 "register_operand" "%0") - (match_operand:QI 2 "register_operand" "r")))] +(define_insn "xor<mode>3" + [(set (match_operand:BW 0 "register_operand" "=r") + (xor:BW (match_operand:BW 1 "register_operand" "%0") + (match_operand:BW 2 "register_operand" "r")))] "" "xor %2,%0" [(set_attr "slottable" "yes") @@ -3118,11 +2373,10 @@ "register_operand" "0"))) (use (match_dup 2))])] "" - " { operands[2] = gen_reg_rtx (SImode); operands[3] = GEN_INT (1 << 31); -}") +}) (define_insn "*expanded_negsf2" [(set (match_operand:SF 0 "register_operand" "=r") @@ -3135,30 +2389,17 @@ ;; No "negdi2" although we could make one up that may be faster than ;; the one in libgcc. -(define_insn "negsi2" - [(set (match_operand:SI 0 "register_operand" "=r") - (neg:SI (match_operand:SI 1 "register_operand" "r")))] - "" - "neg.d %1,%0" - [(set_attr "slottable" "yes")]) - -(define_insn "neghi2" - [(set (match_operand:HI 0 "register_operand" "=r") - (neg:HI (match_operand:HI 1 "register_operand" "r")))] - "" - "neg.w %1,%0" - [(set_attr "slottable" "yes")]) - -(define_insn "negqi2" - [(set (match_operand:QI 0 "register_operand" "=r") - (neg:QI (match_operand:QI 1 "register_operand" "r")))] +(define_insn "neg<mode>2" + [(set (match_operand:BWD 0 "register_operand" "=r") + (neg:BWD (match_operand:BWD 1 "register_operand" "r")))] "" - "neg.b %1,%0" + "neg<m> %1,%0" [(set_attr "slottable" "yes")]) ;; One-complements. ;; See comment on anddi3 - no need for a DImode pattern. +;; See also xor comment. (define_insn "one_cmplsi2" [(set (match_operand:SI 0 "register_operand" "=r") @@ -3167,36 +2408,27 @@ "not %0" [(set_attr "slottable" "yes")]) -(define_insn "one_cmplhi2" - [(set (match_operand:HI 0 "register_operand" "=r") - (not:HI (match_operand:HI 1 "register_operand" "0")))] - "" - "not %0" - [(set_attr "slottable" "yes") - (set_attr "cc" "clobber")]) - -(define_insn "one_cmplqi2" - [(set (match_operand:QI 0 "register_operand" "=r") - (not:QI (match_operand:QI 1 "register_operand" "0")))] +(define_insn "one_cmpl<mode>2" + [(set (match_operand:BW 0 "register_operand" "=r") + (not:BW (match_operand:BW 1 "register_operand" "0")))] "" "not %0" [(set_attr "slottable" "yes") (set_attr "cc" "clobber")]) -;; Arithmetic shift right. +;; Arithmetic/Logical shift right (and SI left). -(define_insn "ashrsi3" +(define_insn "<shlr>si3" [(set (match_operand:SI 0 "register_operand" "=r") - (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "nonmemory_operand" "Kr")))] + (shift:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "nonmemory_operand" "Kr")))] "" - "* { if (REG_S_P (operands[2])) - return \"asr.d %2,%0\"; + return "<slr>.d %2,%0"; - return \"asrq %2,%0\"; -}" + return "<slr>q %2,%0"; +} [(set_attr "slottable" "yes")]) ;; Since gcc gets lost, and forgets to zero-extend the source (or mask @@ -3207,237 +2439,86 @@ ;; FIXME: Is this legacy or still true for gcc >= 2.7.2? -(define_expand "ashrhi3" - [(set (match_dup 3) - (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm"))) - (set (match_dup 4) - (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rm"))) - (set (match_dup 5) (ashiftrt:SI (match_dup 3) (match_dup 4))) - (set (match_operand:HI 0 "general_operand" "=g") - (subreg:HI (match_dup 5) 0))] - "" - " -{ - int i; - - for (i = 3; i < 6; i++) - operands[i] = gen_reg_rtx (SImode); -}") - -(define_insn "*expanded_ashrhi" - [(set (match_operand:HI 0 "register_operand" "=r") - (ashiftrt:HI (match_operand:HI 1 "register_operand" "0") - (match_operand:HI 2 "register_operand" "r")))] - "" - "asr.w %2,%0" - [(set_attr "slottable" "yes")]) - -(define_insn "*ashrhi_lowpart" - [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r")) - (ashiftrt:HI (match_dup 0) - (match_operand:HI 1 "register_operand" "r")))] - "" - "asr.w %1,%0" - [(set_attr "slottable" "yes")]) - -;; Same comment goes as for "ashrhi3". - -(define_expand "ashrqi3" +;; FIXME: Can't parametrize sign_extend and zero_extend (before +;; mentioning "shiftrt"), so we need two patterns. +(define_expand "ashr<mode>3" [(set (match_dup 3) - (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g"))) + (sign_extend:SI (match_operand:BW 1 "nonimmediate_operand" ""))) (set (match_dup 4) - (zero_extend:SI (match_operand:QI 2 "nonimmediate_operand" "g"))) + (zero_extend:SI (match_operand:BW 2 "nonimmediate_operand" ""))) (set (match_dup 5) (ashiftrt:SI (match_dup 3) (match_dup 4))) - (set (match_operand:QI 0 "general_operand" "=g") - (subreg:QI (match_dup 5) 0))] + (set (match_operand:BW 0 "general_operand" "") + (subreg:BW (match_dup 5) 0))] "" - " { int i; for (i = 3; i < 6; i++) operands[i] = gen_reg_rtx (SImode); -}") - -(define_insn "*expanded_ashrqi" - [(set (match_operand:QI 0 "register_operand" "=r") - (ashiftrt:QI (match_operand:QI 1 "register_operand" "0") - (match_operand:QI 2 "register_operand" "r")))] - "" - "asr.b %2,%0" - [(set_attr "slottable" "yes")]) - -;; A strict_low_part matcher. - -(define_insn "*ashrqi_lowpart" - [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r")) - (ashiftrt:QI (match_dup 0) - (match_operand:QI 1 "register_operand" "r")))] - "" - "asr.b %1,%0" - [(set_attr "slottable" "yes")]) - -;; Logical shift right. - -(define_insn "lshrsi3" - [(set (match_operand:SI 0 "register_operand" "=r") - (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "nonmemory_operand" "Kr")))] - "" - "* -{ - if (REG_S_P (operands[2])) - return \"lsr.d %2,%0\"; - - return \"lsrq %2,%0\"; -}" - [(set_attr "slottable" "yes")]) - -;; Same comments as for ashrhi3. - -(define_expand "lshrhi3" - [(set (match_dup 3) - (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g"))) - (set (match_dup 4) - (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "g"))) - (set (match_dup 5) (lshiftrt:SI (match_dup 3) (match_dup 4))) - (set (match_operand:HI 0 "general_operand" "=g") - (subreg:HI (match_dup 5) 0))] - "" - " -{ - int i; - - for (i = 3; i < 6; i++) - operands[i] = gen_reg_rtx (SImode); -}") - -(define_insn "*expanded_lshrhi" - [(set (match_operand:HI 0 "register_operand" "=r") - (lshiftrt:HI (match_operand:HI 1 "register_operand" "0") - (match_operand:HI 2 "register_operand" "r")))] - "" - "lsr.w %2,%0" - [(set_attr "slottable" "yes")]) - -;; A strict_low_part matcher. - -(define_insn "*lshrhi_lowpart" - [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r")) - (lshiftrt:HI (match_dup 0) - (match_operand:HI 1 "register_operand" "r")))] - "" - "lsr.w %1,%0" - [(set_attr "slottable" "yes")]) - -;; Same comments as for ashrhi3. +}) -(define_expand "lshrqi3" +(define_expand "lshr<mode>3" [(set (match_dup 3) - (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g"))) + (zero_extend:SI (match_operand:BW 1 "nonimmediate_operand" ""))) (set (match_dup 4) - (zero_extend:SI (match_operand:QI 2 "nonimmediate_operand" "g"))) + (zero_extend:SI (match_operand:BW 2 "nonimmediate_operand" ""))) (set (match_dup 5) (lshiftrt:SI (match_dup 3) (match_dup 4))) - (set (match_operand:QI 0 "general_operand" "=g") - (subreg:QI (match_dup 5) 0))] + (set (match_operand:BW 0 "general_operand" "") + (subreg:BW (match_dup 5) 0))] "" - " { int i; for (i = 3; i < 6; i++) operands[i] = gen_reg_rtx (SImode); -}") +}) -(define_insn "*expanded_lshrqi" - [(set (match_operand:QI 0 "register_operand" "=r") - (lshiftrt:QI (match_operand:QI 1 "register_operand" "0") - (match_operand:QI 2 "register_operand" "r")))] +(define_insn "*expanded_<shlr><mode>" + [(set (match_operand:BW 0 "register_operand" "=r") + (shiftrt:BW (match_operand:BW 1 "register_operand" "0") + (match_operand:BW 2 "register_operand" "r")))] "" - "lsr.b %2,%0" + "<slr><m> %2,%0" [(set_attr "slottable" "yes")]) -;; A strict_low_part matcher. - -(define_insn "*lshrqi_lowpart" - [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r")) - (lshiftrt:QI (match_dup 0) - (match_operand:QI 1 "register_operand" "r")))] +(define_insn "*<shlr><mode>_lowpart" + [(set (strict_low_part (match_operand:BW 0 "register_operand" "+r")) + (shiftrt:BW (match_dup 0) + (match_operand:BW 1 "register_operand" "r")))] "" - "lsr.b %1,%0" + "<slr><m> %1,%0" [(set_attr "slottable" "yes")]) ;; Arithmetic/logical shift left. -(define_insn "ashlsi3" - [(set (match_operand:SI 0 "register_operand" "=r") - (ashift:SI (match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "nonmemory_operand" "Kr")))] - "" - "* -{ - if (REG_S_P (operands[2])) - return \"lsl.d %2,%0\"; - - return \"lslq %2,%0\"; -}" - [(set_attr "slottable" "yes")]) - ;; For narrower modes than SI, we can use lslq although it makes cc ;; unusable. The win is that we do not have to reload the shift-count ;; into a register. -(define_insn "ashlhi3" - [(set (match_operand:HI 0 "register_operand" "=r,r") - (ashift:HI (match_operand:HI 1 "register_operand" "0,0") - (match_operand:HI 2 "nonmemory_operand" "r,K")))] - "" - "* -{ - return - (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 15) - ? \"moveq 0,%0\" - : (CONSTANT_P (operands[2]) - ? \"lslq %2,%0\" : \"lsl.w %2,%0\"); -}" - [(set_attr "slottable" "yes") - (set_attr "cc" "normal,clobber")]) - -;; A strict_low_part matcher. - -(define_insn "*ashlhi_lowpart" - [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r")) - (ashift:HI (match_dup 0) - (match_operand:HI 1 "register_operand" "r")))] +(define_insn "ashl<mode>3" + [(set (match_operand:BW 0 "register_operand" "=r,r") + (ashift:BW (match_operand:BW 1 "register_operand" "0,0") + (match_operand:BW 2 "nonmemory_operand" "r,K")))] "" - "lsl.w %1,%0" - [(set_attr "slottable" "yes")]) - -(define_insn "ashlqi3" - [(set (match_operand:QI 0 "register_operand" "=r,r") - (ashift:QI (match_operand:QI 1 "register_operand" "0,0") - (match_operand:QI 2 "nonmemory_operand" "r,K")))] - "" - "* { return (GET_CODE (operands[2]) == CONST_INT - && INTVAL (operands[2]) > 7) - ? \"moveq 0,%0\" + && INTVAL (operands[2]) > <nbitsm1>) + ? "moveq 0,%0" : (CONSTANT_P (operands[2]) - ? \"lslq %2,%0\" : \"lsl.b %2,%0\"); -}" + ? "lslq %2,%0" : "lsl<m> %2,%0"); +} [(set_attr "slottable" "yes") (set_attr "cc" "normal,clobber")]) ;; A strict_low_part matcher. -(define_insn "*ashlqi_lowpart" - [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r")) - (ashift:QI (match_dup 0) - (match_operand:QI 1 "register_operand" "r")))] +(define_insn "*ashl<mode>_lowpart" + [(set (strict_low_part (match_operand:BW 0 "register_operand" "+r")) + (ashift:BW (match_dup 0) + (match_operand:HI 1 "register_operand" "r")))] "" - "lsl.b %1,%0" + "lsl<m> %1,%0" [(set_attr "slottable" "yes")]) ;; Various strange insns that gcc likes. @@ -3460,21 +2541,12 @@ ;; FIXME: GCC should be able to do these expansions itself. -(define_expand "abshi2" - [(set (match_dup 2) - (sign_extend:SI (match_operand:HI 1 "general_operand" "g"))) - (set (match_dup 3) (abs:SI (match_dup 2))) - (set (match_operand:HI 0 "register_operand" "=r") - (subreg:HI (match_dup 3) 0))] - "" - "operands[2] = gen_reg_rtx (SImode); operands[3] = gen_reg_rtx (SImode);") - -(define_expand "absqi2" +(define_expand "abs<mode>2" [(set (match_dup 2) - (sign_extend:SI (match_operand:QI 1 "general_operand" "g"))) + (sign_extend:SI (match_operand:BW 1 "general_operand" ""))) (set (match_dup 3) (abs:SI (match_dup 2))) - (set (match_operand:QI 0 "register_operand" "=r") - (subreg:QI (match_dup 3) 0))] + (set (match_operand:BW 0 "register_operand" "") + (subreg:BW (match_dup 3) 0))] "" "operands[2] = gen_reg_rtx (SImode); operands[3] = gen_reg_rtx (SImode);") @@ -3487,21 +2559,20 @@ (umin:SI (match_operand:SI 1 "register_operand" "%0,0, 0,r") (match_operand:SI 2 "general_operand" "r,Q>,g,!STo")))] "" - "* { if (GET_CODE (operands[2]) == CONST_INT) { if (INTVAL (operands[2]) < 256) - return \"bound.b %2,%0\"; + return "bound.b %2,%0"; if (INTVAL (operands[2]) < 65536) - return \"bound.w %2,%0\"; + return "bound.w %2,%0"; } else if (which_alternative == 3) - return \"bound.d %2,%1,%0\"; + return "bound.d %2,%1,%0"; - return \"bound.d %2,%0\"; -}" + return "bound.d %2,%0"; +} [(set_attr "slottable" "yes,yes,no,no")]) ;; Jump and branch insns. @@ -3567,246 +2638,82 @@ ;; e.g. m68k, so we have to check if overflow bit is set on all "signed" ;; conditions. -(define_insn "beq" - [(set (pc) - (if_then_else (eq (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "beq %l0%#" - [(set_attr "slottable" "has_slot")]) - -(define_insn "bne" - [(set (pc) - (if_then_else (ne (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "bne %l0%#" - [(set_attr "slottable" "has_slot")]) - -(define_insn "bgt" - [(set (pc) - (if_then_else (gt (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "* -{ - return - (cc_prev_status.flags & CC_NO_OVERFLOW) - ? 0 : \"bgt %l0%#\"; -}" - [(set_attr "slottable" "has_slot")]) - -(define_insn "bgtu" - [(set (pc) - (if_then_else (gtu (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "bhi %l0%#" - [(set_attr "slottable" "has_slot")]) - -(define_insn "blt" +(define_insn "b<ncond>" [(set (pc) - (if_then_else (lt (cc0) - (const_int 0)) + (if_then_else (ncond (cc0) + (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" - "* -{ - return - (cc_prev_status.flags & CC_NO_OVERFLOW) - ? \"bmi %l0%#\" : \"blt %l0%#\"; -}" + "b<CC> %l0%#" [(set_attr "slottable" "has_slot")]) -(define_insn "bltu" +(define_insn "b<ocond>" [(set (pc) - (if_then_else (ltu (cc0) - (const_int 0)) + (if_then_else (ocond (cc0) + (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" - "blo %l0%#" - [(set_attr "slottable" "has_slot")]) - -(define_insn "bge" - [(set (pc) - (if_then_else (ge (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "* { return (cc_prev_status.flags & CC_NO_OVERFLOW) - ? \"bpl %l0%#\" : \"bge %l0%#\"; -}" - [(set_attr "slottable" "has_slot")]) - -(define_insn "bgeu" - [(set (pc) - (if_then_else (geu (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "bhs %l0%#" + ? 0 : \"b<CC> %l0%#\"; +} [(set_attr "slottable" "has_slot")]) -(define_insn "ble" +(define_insn "b<rcond>" [(set (pc) - (if_then_else (le (cc0) - (const_int 0)) + (if_then_else (rcond (cc0) + (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" - "* { return (cc_prev_status.flags & CC_NO_OVERFLOW) - ? 0 : \"ble %l0%#\"; -}" - [(set_attr "slottable" "has_slot")]) - -(define_insn "bleu" - [(set (pc) - (if_then_else (leu (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "bls %l0%#" + ? "b<oCC> %l0%#" : "b<CC> %l0%#"; +} [(set_attr "slottable" "has_slot")]) ;; Reversed anonymous patterns to the ones above, as mandated. -(define_insn "*beq_reversed" - [(set (pc) - (if_then_else (eq (cc0) - (const_int 0)) - (pc) - (label_ref (match_operand 0 "" ""))))] - "" - "bne %l0%#" - [(set_attr "slottable" "has_slot")]) - -(define_insn "*bne_reversed" - [(set (pc) - (if_then_else (ne (cc0) - (const_int 0)) - (pc) - (label_ref (match_operand 0 "" ""))))] - "" - "beq %l0%#" - [(set_attr "slottable" "has_slot")]) - -(define_insn "*bgt_reversed" - [(set (pc) - (if_then_else (gt (cc0) - (const_int 0)) - (pc) - (label_ref (match_operand 0 "" ""))))] - "" - "* -{ - return - (cc_prev_status.flags & CC_NO_OVERFLOW) - ? 0 : \"ble %l0%#\"; -}" - [(set_attr "slottable" "has_slot")]) - -(define_insn "*bgtu_reversed" - [(set (pc) - (if_then_else (gtu (cc0) - (const_int 0)) - (pc) - (label_ref (match_operand 0 "" ""))))] - "" - "bls %l0%#" - [(set_attr "slottable" "has_slot")]) - -(define_insn "*blt_reversed" +(define_insn "*b<ncond>_reversed" [(set (pc) - (if_then_else (lt (cc0) - (const_int 0)) + (if_then_else (ncond (cc0) + (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" - "* -{ - return - (cc_prev_status.flags & CC_NO_OVERFLOW) - ? \"bpl %l0%#\" : \"bge %l0%#\"; -}" + "b<rCC> %l0%#" [(set_attr "slottable" "has_slot")]) -(define_insn "*bltu_reversed" +(define_insn "*b<ocond>_reversed" [(set (pc) - (if_then_else (ltu (cc0) - (const_int 0)) + (if_then_else (ocond (cc0) + (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" - "bhs %l0%#" - [(set_attr "slottable" "has_slot")]) - -(define_insn "*bge_reversed" - [(set (pc) - (if_then_else (ge (cc0) - (const_int 0)) - (pc) - (label_ref (match_operand 0 "" ""))))] - "" - "* { return (cc_prev_status.flags & CC_NO_OVERFLOW) - ? \"bmi %l0%#\" : \"blt %l0%#\"; -}" - [(set_attr "slottable" "has_slot")]) - -(define_insn "*bgeu_reversed" - [(set (pc) - (if_then_else (geu (cc0) - (const_int 0)) - (pc) - (label_ref (match_operand 0 "" ""))))] - "" - "blo %l0%#" + ? 0 : \"b<rCC> %l0%#\"; +} [(set_attr "slottable" "has_slot")]) -(define_insn "*ble_reversed" +(define_insn "*b<rcond>_reversed" [(set (pc) - (if_then_else (le (cc0) - (const_int 0)) + (if_then_else (rcond (cc0) + (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] "" - "* { return (cc_prev_status.flags & CC_NO_OVERFLOW) - ? 0 : \"bgt %l0%#\"; -}" - [(set_attr "slottable" "has_slot")]) - -(define_insn "*bleu_reversed" - [(set (pc) - (if_then_else (leu (cc0) - (const_int 0)) - (pc) - (label_ref (match_operand 0 "" ""))))] - "" - "bhi %l0%#" + ? \"b<roCC> %l0%#\" : \"b<rCC> %l0%#\"; +} [(set_attr "slottable" "has_slot")]) ;; Set on condition: sCC. @@ -3814,103 +2721,35 @@ ;; Like bCC, we have to check the overflow bit for ;; signed conditions. -(define_insn "sgeu" - [(set (match_operand:SI 0 "register_operand" "=r") - (geu:SI (cc0) (const_int 0)))] - "" - "shs %0" - [(set_attr "slottable" "yes") - (set_attr "cc" "none")]) - -(define_insn "sltu" - [(set (match_operand:SI 0 "register_operand" "=r") - (ltu:SI (cc0) (const_int 0)))] - "" - "slo %0" - [(set_attr "slottable" "yes") - (set_attr "cc" "none")]) - -(define_insn "seq" - [(set (match_operand:SI 0 "register_operand" "=r") - (eq:SI (cc0) (const_int 0)))] - "" - "seq %0" - [(set_attr "slottable" "yes") - (set_attr "cc" "none")]) - -(define_insn "sge" - [(set (match_operand:SI 0 "register_operand" "=r") - (ge:SI (cc0) (const_int 0)))] - "" - "* -{ - return - (cc_prev_status.flags & CC_NO_OVERFLOW) - ? \"spl %0\" : \"sge %0\"; -}" - [(set_attr "slottable" "yes") - (set_attr "cc" "none")]) - -(define_insn "sgt" +(define_insn "s<ncond>" [(set (match_operand:SI 0 "register_operand" "=r") - (gt:SI (cc0) (const_int 0)))] + (ncond:SI (cc0) (const_int 0)))] "" - "* -{ - return - (cc_prev_status.flags & CC_NO_OVERFLOW) - ? 0 : \"sgt %0\"; -}" + "s<CC> %0" [(set_attr "slottable" "yes") (set_attr "cc" "none")]) -(define_insn "sgtu" +(define_insn "s<rcond>" [(set (match_operand:SI 0 "register_operand" "=r") - (gtu:SI (cc0) (const_int 0)))] + (rcond:SI (cc0) (const_int 0)))] "" - "shi %0" - [(set_attr "slottable" "yes") - (set_attr "cc" "none")]) - -(define_insn "sle" - [(set (match_operand:SI 0 "register_operand" "=r") - (le:SI (cc0) (const_int 0)))] - "" - "* { return (cc_prev_status.flags & CC_NO_OVERFLOW) - ? 0 : \"sle %0\"; -}" - [(set_attr "slottable" "yes") - (set_attr "cc" "none")]) - -(define_insn "sleu" - [(set (match_operand:SI 0 "register_operand" "=r") - (leu:SI (cc0) (const_int 0)))] - "" - "sls %0" + ? "s<oCC> %0" : "s<CC> %0"; +} [(set_attr "slottable" "yes") (set_attr "cc" "none")]) -(define_insn "slt" +(define_insn "s<ocond>" [(set (match_operand:SI 0 "register_operand" "=r") - (lt:SI (cc0) (const_int 0)))] + (ocond:SI (cc0) (const_int 0)))] "" - "* { return (cc_prev_status.flags & CC_NO_OVERFLOW) - ? \"smi %0\" : \"slt %0\"; -}" - [(set_attr "slottable" "yes") - (set_attr "cc" "none")]) - -(define_insn "sne" - [(set (match_operand:SI 0 "register_operand" "=r") - (ne:SI (cc0) (const_int 0)))] - "" - "sne %0" + ? 0 : "s<CC> %0"; +} [(set_attr "slottable" "yes") (set_attr "cc" "none")]) @@ -4103,13 +2942,12 @@ (label_ref (match_operand 4 "" "")))) (use (label_ref (match_operand 3 "" "")))])] "" - " { operands[2] = plus_constant (operands[2], 1); operands[5] = gen_reg_rtx (SImode); operands[6] = gen_reg_rtx (SImode); operands[7] = gen_reg_rtx (SImode); -}") +}) ;; Split-patterns. Some of them have modes unspecified. This ;; should always be ok; if for no other reason sparc.md has it as @@ -4412,11 +3250,11 @@ (set (match_dup 5) (match_dup 2))] "operands[5] = replace_equiv_address (operands[6], operands[3]);") -;; clear.d [rx=rx+rz.S2] +;; clear.[bwd] [rx=rx+rz.S2] (define_split [(parallel - [(set (mem:SI (plus:SI + [(set (mem:BWD (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "") (match_operand:SI 1 "const_int_operand" "")) (match_operand:SI 2 "register_operand" ""))) @@ -4429,88 +3267,14 @@ && REGNO (operands[3]) == REGNO (operands[2])" [(set (match_dup 3) (plus:SI (mult:SI (match_dup 0) (match_dup 1)) (match_dup 2))) - (set (mem:SI (match_dup 3)) (const_int 0))] - "") - -;; clear.w [rx=rx+rz.S2] - -(define_split - [(parallel - [(set (mem:HI (plus:SI - (mult:SI (match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "const_int_operand" "")) - (match_operand:SI 2 "register_operand" ""))) - (const_int 0)) - (set (match_operand:SI 3 "register_operand" "") - (plus:SI (mult:SI (match_dup 0) - (match_dup 1)) - (match_dup 2)))])] - "REG_P (operands[2]) && REG_P (operands[3]) - && REGNO (operands[3]) == REGNO (operands[2])" - [(set (match_dup 3) (plus:SI (mult:SI (match_dup 0) (match_dup 1)) - (match_dup 2))) - (set (mem:HI (match_dup 3)) (const_int 0))] - "") - -;; clear.b [rx=rx+rz.S2] - -(define_split - [(parallel - [(set (mem:QI (plus:SI - (mult:SI (match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "const_int_operand" "")) - (match_operand:SI 2 "register_operand" ""))) - (const_int 0)) - (set (match_operand:SI 3 "register_operand" "") - (plus:SI (mult:SI (match_dup 0) - (match_dup 1)) - (match_dup 2)))])] - "REG_P (operands[2]) && REG_P (operands[3]) - && REGNO (operands[3]) == REGNO (operands[2])" - [(set (match_dup 3) (plus:SI (mult:SI (match_dup 0) (match_dup 1)) - (match_dup 2))) - (set (mem:QI (match_dup 3)) (const_int 0))] - "") - -;; clear.d [rx=rx+i] - -(define_split - [(parallel - [(set (mem:SI - (plus:SI (match_operand:SI 0 "cris_bdap_operand" "") - (match_operand:SI 1 "cris_bdap_operand" ""))) - (const_int 0)) - (set (match_operand:SI 2 "register_operand" "") - (plus:SI (match_dup 0) - (match_dup 1)))])] - "(rtx_equal_p (operands[0], operands[2]) - || rtx_equal_p (operands[2], operands[1]))" - [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1))) - (set (mem:SI (match_dup 2)) (const_int 0))] - "") - -;; clear.w [rx=rx+i] - -(define_split - [(parallel - [(set (mem:HI - (plus:SI (match_operand:SI 0 "cris_bdap_operand" "") - (match_operand:SI 1 "cris_bdap_operand" ""))) - (const_int 0)) - (set (match_operand:SI 2 "register_operand" "") - (plus:SI (match_dup 0) - (match_dup 1)))])] - "(rtx_equal_p (operands[0], operands[2]) - || rtx_equal_p (operands[2], operands[1]))" - [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1))) - (set (mem:HI (match_dup 2)) (const_int 0))] + (set (mem:BWD (match_dup 3)) (const_int 0))] "") -;; clear.b [rx=rx+i] +;; clear.[bwd] [rx=rx+i] (define_split [(parallel - [(set (mem:QI + [(set (mem:BWD (plus:SI (match_operand:SI 0 "cris_bdap_operand" "") (match_operand:SI 1 "cris_bdap_operand" ""))) (const_int 0)) @@ -4520,7 +3284,7 @@ "(rtx_equal_p (operands[0], operands[2]) || rtx_equal_p (operands[2], operands[1]))" [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1))) - (set (mem:QI (match_dup 2)) (const_int 0))] + (set (mem:BWD (match_dup 2)) (const_int 0))] "") ;; mov(s|u).S1 [rx=rx+rz.S2],ry |