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| author | liuhongt <hongtao.liu@intel.com> | 2022-04-28 15:30:06 +0800 |
|---|---|---|
| committer | liuhongt <hongtao.liu@intel.com> | 2022-05-18 10:56:35 +0800 |
| commit | 102237c9f2f2667eb73cb5473bd3a9a97296a414 (patch) | |
| tree | ee8852976fdd32aac827579af440bf4bcaa6e3f2 /gcc | |
| parent | 850a13d754497faae91afabc6958780f1d63a574 (diff) | |
| download | gcc-102237c9f2f2667eb73cb5473bd3a9a97296a414.zip gcc-102237c9f2f2667eb73cb5473bd3a9a97296a414.tar.gz gcc-102237c9f2f2667eb73cb5473bd3a9a97296a414.tar.bz2 | |
recognize bzhi pattern when there's zero_extendsidi.
backend has
16550(define_insn "*bmi2_bzhi_<mode>3_2"
16551 [(set (match_operand:SWI48 0 "register_operand" "=r")
16552 (and:SWI48
16553 (plus:SWI48
16554 (ashift:SWI48 (const_int 1)
16555 (match_operand:QI 2 "register_operand" "r"))
16556 (const_int -1))
16557 (match_operand:SWI48 1 "nonimmediate_operand" "rm")))
16558 (clobber (reg:CC FLAGS_REG))]
16559 "TARGET_BMI2"
16560 "bzhi\t{%<k>2, %1, %0|%0, %1, %<k>2}"
16561 [(set_attr "type" "bitmanip")
16562 (set_attr "prefix" "vex")
16563 (set_attr "mode" "<MODE>")])
But there's extra zero_extend in pattern match.
424Failed to match this instruction:
425(parallel [
426 (set (reg:DI 90)
427 (zero_extend:DI (and:SI (plus:SI (ashift:SI (const_int 1 [0x1])
428 (subreg:QI (reg:SI 98) 0))
429 (const_int -1 [0xffffffffffffffff]))
430 (subreg:SI (reg:DI 95) 0))))
431 (clobber (reg:CC 17 flags))
432 ])
Add new define_insn for it.
gcc/ChangeLog:
PR target/104375
* config/i386/i386.md (*bmi2_bzhi_zero_extendsidi_4): New
define_insn.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr104375.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/i386/i386.md | 16 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr104375.c | 9 |
2 files changed, 25 insertions, 0 deletions
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 76bb565..80fc6c9 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -16652,6 +16652,22 @@ (set_attr "prefix" "vex") (set_attr "mode" "<MODE>")]) +(define_insn "*bmi2_bzhi_zero_extendsidi_4" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (and:SI + (plus:SI + (ashift:SI (const_int 1) + (match_operand:QI 2 "register_operand" "r")) + (const_int -1)) + (match_operand:SI 1 "nonimmediate_operand" "rm")))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_64BIT && TARGET_BMI2" + "bzhi\t{%q2, %q1, %q0|%q0, %q1, %q2}" + [(set_attr "type" "bitmanip") + (set_attr "prefix" "vex") + (set_attr "mode" "DI")]) + (define_insn "bmi2_pdep_<mode>3" [(set (match_operand:SWI48 0 "register_operand" "=r") (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r") diff --git a/gcc/testsuite/gcc.target/i386/pr104375.c b/gcc/testsuite/gcc.target/i386/pr104375.c new file mode 100644 index 0000000..5c9f511 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr104375.c @@ -0,0 +1,9 @@ +#/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mbmi2 -O2" } */ +/* { dg-final { scan-assembler-times {(?n)shrx[\t ]+} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)bzhi[\t ]+} 1 } } */ + +unsigned long long bextr_u64(unsigned long long w, unsigned off, unsigned int len) +{ + return (w >> off) & ((1U << len) - 1U); +} |