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| author | H.J. Lu <hongjiu.lu@intel.com> | 2019-02-11 01:39:54 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2019-02-10 17:39:54 -0800 |
| commit | 8d75ab4d5ccb43ad0411ebd976e757895f45d4a7 (patch) | |
| tree | aa7d5bcb94b4508ad3410519dafce1eb96af72a7 /gcc | |
| parent | 05eca5117595ced9bbe1d95e67d2b1a92f393ea1 (diff) | |
| download | gcc-8d75ab4d5ccb43ad0411ebd976e757895f45d4a7.zip gcc-8d75ab4d5ccb43ad0411ebd976e757895f45d4a7.tar.gz gcc-8d75ab4d5ccb43ad0411ebd976e757895f45d4a7.tar.bz2 | |
i386: Fix a typo in comments for for "Yd"
config/i386/constraints.md has
(define_register_constraint "Yd"
"TARGET_AVX512DQ ? ALL_SSE_REGS : TARGET_SSE4_1 ? SSE_REGS : NO_REGS"
"@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target.")
Comments for "Yd" should mention AVX512DQ, not AVX512BW.
* config/i386/constraints.md (Yd): Replace AVX512BW with AVX512DQ
in comments
From-SVN: r268759
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/i386/constraints.md | 2 |
2 files changed, 6 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index aea089f..1df0ce9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2019-02-10 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/constraints.md (Yd): Replace AVX512BW with AVX512DQ + in comments + 2019-02-10 Chung-Ju Wu <jasonwucj@gmail.com> * config.gcc (with_nds32_lib): Set default --with-nds32-lib correctly. diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md index 33921ae..16075b4 100644 --- a/gcc/config/i386/constraints.md +++ b/gcc/config/i386/constraints.md @@ -96,7 +96,7 @@ ;; We use the Y prefix to denote any number of conditional register sets: ;; z First SSE register. -;; d any EVEX encodable SSE register for AVX512BW target or +;; d any EVEX encodable SSE register for AVX512DQ target or ;; any SSE register for SSE4_1 target. ;; p Integer register when TARGET_PARTIAL_REG_STALL is disabled ;; a Integer register when zero extensions with AND are disabled |