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author | John David Anglin <danglin@gcc.gnu.org> | 2015-02-15 15:18:47 +0000 |
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committer | John David Anglin <danglin@gcc.gnu.org> | 2015-02-15 15:18:47 +0000 |
commit | feb675e4087d78e3a3a47d57a220773d80a6d747 (patch) | |
tree | 468ceea4174a24c448ee4a2c7af0da90d6d9046d /gcc | |
parent | dbf73e6e286d145ad3032c6efe0c9c35abd6ce63 (diff) | |
download | gcc-feb675e4087d78e3a3a47d57a220773d80a6d747.zip gcc-feb675e4087d78e3a3a47d57a220773d80a6d747.tar.gz gcc-feb675e4087d78e3a3a47d57a220773d80a6d747.tar.bz2 |
pa.c (pa_secondary_reload): Request a secondary reload for all floading point loads and stores except those...
* config/pa/pa.c (pa_secondary_reload): Request a secondary reload
for all floading point loads and stores except those using a register
index address.
* config/pa/pa.md: Add new patterns to load a lo_sum DLT operand
to a register.
From-SVN: r220716
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/ChangeLog | 8 | ||||
-rw-r--r-- | gcc/config/pa/pa.c | 19 | ||||
-rw-r--r-- | gcc/config/pa/pa.md | 23 |
3 files changed, 39 insertions, 11 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 79ba74d..71822aa 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2015-02-15 John David Anglin <danglin@gcc.gnu.org> + + * config/pa/pa.c (pa_secondary_reload): Request a secondary reload + for all floading point loads and stores except those using a register + index address. + * config/pa/pa.md: Add new patterns to load a lo_sum DLT operand + to a register. + 2015-02-14 Jan Hubicka <hubicka@ucw.cz> * ipa-inline-analysis.c (growth_data): Add uninlinable field. diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c index 13bd529..15913dc 100644 --- a/gcc/config/pa/pa.c +++ b/gcc/config/pa/pa.c @@ -6031,18 +6031,15 @@ pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, { x = XEXP (x, 0); - /* We don't need an intermediate for indexed and LO_SUM DLT - memory addresses. When INT14_OK_STRICT is true, it might - appear that we could directly allow register indirect - memory addresses. However, this doesn't work because we - don't support SUBREGs in floating-point register copies - and reload doesn't tell us when it's going to use a SUBREG. */ - if (IS_INDEX_ADDR_P (x) - || IS_LO_SUM_DLT_ADDR_P (x)) + /* We don't need a secondary reload for indexed memory addresses. + + When INT14_OK_STRICT is true, it might appear that we could + directly allow register indirect memory addresses. However, + this doesn't work because we don't support SUBREGs in + floating-point register copies and reload doesn't tell us + when it's going to use a SUBREG. */ + if (IS_INDEX_ADDR_P (x)) return NO_REGS; - - /* Request intermediate general register. */ - return GENERAL_REGS; } /* Request a secondary reload with a general scratch register diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index 54e7e68..2fd2059 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -2673,6 +2673,29 @@ [(set_attr "type" "binary") (set_attr "length" "4")]) +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=r") + (lo_sum:SI (match_operand:SI 1 "register_operand" "r") + (unspec:SI [(match_operand 2 "" "")] UNSPEC_DLTIND14R)))] + "symbolic_operand (operands[2], Pmode) + && ! function_label_operand (operands[2], Pmode) + && flag_pic" + "ldo RT'%G2(%1),%0" + [(set_attr "type" "binary") + (set_attr "length" "4")]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=r") + (lo_sum:DI (match_operand:DI 1 "register_operand" "r") + (unspec:DI [(match_operand 2 "" "")] UNSPEC_DLTIND14R)))] + "symbolic_operand (operands[2], Pmode) + && ! function_label_operand (operands[2], Pmode) + && TARGET_64BIT + && flag_pic" + "ldo RT'%G2(%1),%0" + [(set_attr "type" "binary") + (set_attr "length" "4")]) + ;; Always use addil rather than ldil;add sequences. This allows the ;; HP linker to eliminate the dp relocation if the symbolic operand ;; lives in the TEXT space. |