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| author | James E Wilson <wilson@tuliptree.org> | 2003-06-10 21:25:47 -0700 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 2003-06-10 21:25:47 -0700 |
| commit | f58d8c95968d3ba7e1ceca2e9cb799ee26c941a2 (patch) | |
| tree | a25acc52909f923cf8d78ae5442aa4e4419df108 /gcc | |
| parent | 46dfb7aa2cdcc6125a2f17cd38fee0f4b1b21503 (diff) | |
| download | gcc-f58d8c95968d3ba7e1ceca2e9cb799ee26c941a2.zip gcc-f58d8c95968d3ba7e1ceca2e9cb799ee26c941a2.tar.gz gcc-f58d8c95968d3ba7e1ceca2e9cb799ee26c941a2.tar.bz2 | |
re PR rtl-optimization/8812 ([avr] Registers allocated for two uses at once)
PR target/8812
* reload1.c (choose_reload_regs): For equiv reg, add loop over all
hard regs for reload_reg_used_at_all and reg_class_contents checks.
From-SVN: r67751
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/reload1.c | 23 |
2 files changed, 24 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5035995..2fcaf5a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2003-06-10 James E Wilson <wilson@tuliptree.org> + + PR target/8812 + * reload1.c (choose_reload_regs): For equiv reg, add loop over all + hard regs for reload_reg_used_at_all and reg_class_contents checks. + 2003-06-10 Kazu Hirata <kazu@cs.umass.edu> * config/h8300/h8300.c (print_operand): Remove support for diff --git a/gcc/reload1.c b/gcc/reload1.c index 79ce9a1..f8b3d5a 100644 --- a/gcc/reload1.c +++ b/gcc/reload1.c @@ -5685,14 +5685,27 @@ choose_reload_regs (chain) /* If we found a spill reg, reject it unless it is free and of the desired class. */ - if (equiv != 0 - && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno) + if (equiv != 0) + { + int regs_used = 0; + int bad_for_class = 0; + int max_regno = regno + rld[r].nregs; + + for (i = regno; i < max_regno; i++) + { + regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all, + i); + bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class], + i); + } + + if ((regs_used && ! free_for_value_p (regno, rld[r].mode, rld[r].opnum, rld[r].when_needed, rld[r].in, rld[r].out, r, 1)) - || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class], - regno))) - equiv = 0; + || bad_for_class) + equiv = 0; + } if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode)) equiv = 0; |