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| author | Peter Bergner <bergner@vnet.ibm.com> | 2018-06-08 12:17:45 -0500 |
|---|---|---|
| committer | Peter Bergner <bergner@gcc.gnu.org> | 2018-06-08 12:17:45 -0500 |
| commit | f57d14462e14ca3d33de5d4fd0c9260fa15b2065 (patch) | |
| tree | 1325ba07357ff04c13d13d80f48785d508d329ff /gcc | |
| parent | a14175560cca5da1f9ff776c5c7309473397d43d (diff) | |
| download | gcc-f57d14462e14ca3d33de5d4fd0c9260fa15b2065.zip gcc-f57d14462e14ca3d33de5d4fd0c9260fa15b2065.tar.gz gcc-f57d14462e14ca3d33de5d4fd0c9260fa15b2065.tar.bz2 | |
re PR target/85755 (PowerPC Gcc's -mupdate produces inefficient code on power8/power9 machines)
gcc/
PR target/85755
* config/rs6000/rs6000.c (mem_operand_gpr): Enable PRE_INC and PRE_DEC
addresses.
gcc/testsuite/
PR target/85755
* gcc.target/powerpc/pr85755.c: New test.
From-SVN: r261340
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 7 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/pr85755.c | 22 |
4 files changed, 40 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1e67efc..367e91f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2018-06-08 Peter Bergner <bergner@vnet.ibm.com> + + PR target/85755 + * config/rs6000/rs6000.c (mem_operand_gpr): Enable PRE_INC and PRE_DEC + addresses. + 2018-06-08 Jan Hubicka <hubicka@ucw.cz> * dumpfile.c (FIRST_ME_AUTO_NUMBERED_DUMP): Bump to 4. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 4c447d4..8bc4109 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -7996,6 +7996,13 @@ mem_operand_gpr (rtx op, machine_mode mode) int extra; rtx addr = XEXP (op, 0); + /* PR85755: Allow PRE_INC and PRE_DEC addresses. */ + if (TARGET_UPDATE + && (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC) + && mode_supports_pre_incdec_p (mode) + && legitimate_indirect_address_p (XEXP (addr, 0), false)) + return true; + /* Don't allow non-offsettable addresses. See PRs 83969 and 84279. */ if (!rs6000_offsettable_memref_p (op, mode, false)) return false; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index af9b5d4..3b3bc5a 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-06-08 Peter Bergner <bergner@vnet.ibm.com> + + PR target/85755 + * gcc.target/powerpc/pr85755.c: New test. + 2018-06-08 Carl Love <cel@us.ibm.com> * gcc.target/powerpc/vsx-vector-6-be.p7.c: Rename this file to diff --git a/gcc/testsuite/gcc.target/powerpc/pr85755.c b/gcc/testsuite/gcc.target/powerpc/pr85755.c new file mode 100644 index 0000000..2d8741d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr85755.c @@ -0,0 +1,22 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-options "-O1" } */ + +void +preinc (long *q, long n) +{ + long i; + for (i = 0; i < n; i++) + q[i] = i; +} + +void +predec (long *q, long n) +{ + long i; + for (i = n; i >= 0; i--) + q[i] = i; +} + +/* { dg-final { scan-assembler-times {\mstwu\M} 2 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\mstdu\M} 2 { target lp64 } } } */ +/* { dg-final { scan-assembler-not {\mstfdu\M} } } */ |