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| author | Uros Bizjak <ubizjak@gmail.com> | 2021-07-15 22:34:25 +0200 |
|---|---|---|
| committer | Uros Bizjak <ubizjak@gmail.com> | 2021-07-15 22:40:30 +0200 |
| commit | f364cdffa47af574f90f671b2dcf5afa91442741 (patch) | |
| tree | 3b721531d4c564e51e18dd8476b20f26fb67a1be /gcc | |
| parent | 478cc962ad174bfc64c573152a0658935651fce3 (diff) | |
| download | gcc-f364cdffa47af574f90f671b2dcf5afa91442741.zip gcc-f364cdffa47af574f90f671b2dcf5afa91442741.tar.gz gcc-f364cdffa47af574f90f671b2dcf5afa91442741.tar.bz2 | |
i386: Fix ix86_hard_regno_mode_ok for TDmode on 32bit targets [PR101346]
General regs on 32bit targets do not support 128bit modes,
including TDmode.
gcc/
2021-07-15 Uroš Bizjak <ubizjak@gmail.com>
PR target/101346
* config/i386/i386.h (VALID_SSE_REG_MODE): Add TDmode.
(VALID_INT_MODE_P): Add SDmode and DDmode.
Add TDmode for TARGET_64BIT.
(VALID_DFP_MODE_P): Remove.
* config/i386/i386.c (ix86_hard_regno_mode_ok):
Do not use VALID_DFP_MODE_P.
gcc/testsuite/
2021-07-15 Uroš Bizjak <ubizjak@gmail.com>
PR target/101346
* gcc.target/i386/pr101346.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/i386/i386.c | 7 | ||||
| -rw-r--r-- | gcc/config/i386/i386.h | 8 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr101346.c | 10 |
3 files changed, 15 insertions, 10 deletions
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 530d357..9d74b7a 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -19535,11 +19535,8 @@ ix86_hard_regno_mode_ok (unsigned int regno, machine_mode mode) return !can_create_pseudo_p (); } /* We handle both integer and floats in the general purpose registers. */ - else if (VALID_INT_MODE_P (mode)) - return true; - else if (VALID_FP_MODE_P (mode)) - return true; - else if (VALID_DFP_MODE_P (mode)) + else if (VALID_INT_MODE_P (mode) + || VALID_FP_MODE_P (mode)) return true; /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go on to use that value in smaller contexts, this can easily force a diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 324e8a9..0c2c93d 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -1023,7 +1023,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); #define VALID_SSE_REG_MODE(MODE) \ ((MODE) == V1TImode || (MODE) == TImode \ || (MODE) == V4SFmode || (MODE) == V4SImode \ - || (MODE) == SFmode || (MODE) == TFmode) + || (MODE) == SFmode || (MODE) == TFmode || (MODE) == TDmode) #define VALID_MMX_REG_MODE_3DNOW(MODE) \ ((MODE) == V2SFmode || (MODE) == SFmode) @@ -1037,9 +1037,6 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); #define VALID_MASK_AVX512BW_MODE(MODE) ((MODE) == SImode || (MODE) == DImode) -#define VALID_DFP_MODE_P(MODE) \ - ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) - #define VALID_FP_MODE_P(MODE) \ ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ @@ -1049,12 +1046,13 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); || (MODE) == SImode || (MODE) == DImode \ || (MODE) == CQImode || (MODE) == CHImode \ || (MODE) == CSImode || (MODE) == CDImode \ + || (MODE) == SDmode || (MODE) == DDmode \ || (MODE) == V4QImode || (MODE) == V2HImode || (MODE) == V1SImode \ || (TARGET_64BIT \ && ((MODE) == TImode || (MODE) == CTImode \ || (MODE) == TFmode || (MODE) == TCmode \ || (MODE) == V8QImode || (MODE) == V4HImode \ - || (MODE) == V2SImode))) + || (MODE) == V2SImode || (MODE) == TDmode))) /* Return true for modes passed in SSE registers. */ #define SSE_REG_MODE_P(MODE) \ diff --git a/gcc/testsuite/gcc.target/i386/pr101346.c b/gcc/testsuite/gcc.target/i386/pr101346.c new file mode 100644 index 0000000..fefabaf --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr101346.c @@ -0,0 +1,10 @@ +/* PR target/101346 */ +/* { dg-do compile } */ +/* { dg-options "-O0 -fprofile-generate -msse" } */ +/* { dg-require-profiling "-fprofile-generate" } */ + +_Decimal128 +foo (_Decimal128 x) +{ + return - __builtin_fabsd128 (x); +} |