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| author | Steve Ellcey <sellcey@marvell.com> | 2019-04-11 18:02:41 +0000 |
|---|---|---|
| committer | Steve Ellcey <sje@gcc.gnu.org> | 2019-04-11 18:02:41 +0000 |
| commit | f0a8f6bcb0c491db71fb791e2f5999595a44116e (patch) | |
| tree | 484f83287e54e3cf5248f9216e39fadb2a35201f /gcc | |
| parent | cd7ffd8a9382c78725f3c09b317bdb4739d3654b (diff) | |
| download | gcc-f0a8f6bcb0c491db71fb791e2f5999595a44116e.zip gcc-f0a8f6bcb0c491db71fb791e2f5999595a44116e.tar.gz gcc-f0a8f6bcb0c491db71fb791e2f5999595a44116e.tar.bz2 | |
re PR rtl-optimization/87763 (aarch64 target testcases fail after r265398)
2018-04-11 Steve Ellcey <sellcey@marvell.com>
PR rtl-optimization/87763
* config/aarch64/aarch64.md (*aarch64_bfi<GPI:mode>4_noshift_alt):
New Instruction.
From-SVN: r270288
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 15 |
2 files changed, 20 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index cf4434a..970bdf8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2018-04-11 Steve Ellcey <sellcey@marvell.com> + + PR rtl-optimization/87763 + * config/aarch64/aarch64.md (*aarch64_bfi<GPI:mode>4_noshift_alt): + New Instruction. + 2019-04-11 Tom de Vries <tdevries@suse.de> * doc/extend.texi (@node Statement Exprs): Note variable shadowing at diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index e0df975..5a18940 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -5565,7 +5565,8 @@ ) ;; Like *aarch64_bfi<GPI:mode>5_shift but with no shifting, we are just -;; copying the least significant bits of OP3 to OP0. +;; copying the least significant bits of OP3 to OP0. We need two versions +;; of the instruction to handle different checks on the constant values. (define_insn "*aarch64_bfi<GPI:mode>4_noshift" [(set (match_operand:GPI 0 "register_operand" "=r") @@ -5579,6 +5580,18 @@ [(set_attr "type" "bfm")] ) +(define_insn "*aarch64_bfi<GPI:mode>4_noshift_alt" + [(set (match_operand:GPI 0 "register_operand" "=r") + (ior:GPI (and:GPI (match_operand:GPI 3 "register_operand" "r") + (match_operand:GPI 4 "const_int_operand" "n")) + (and:GPI (match_operand:GPI 1 "register_operand" "0") + (match_operand:GPI 2 "const_int_operand" "n"))))] + "aarch64_masks_and_shift_for_bfi_p (<MODE>mode, UINTVAL (operands[2]), 0, + UINTVAL (operands[4]))" + "bfi\t%<GPI:w>0, %<GPI:w>3, 0, %P4" + [(set_attr "type" "bfm")] +) + (define_insn "*extr_insv_lower_reg<mode>" [(set (zero_extract:GPI (match_operand:GPI 0 "register_operand" "+r") (match_operand 1 "const_int_operand" "n") |