Remove accidentally committed piece of patch.

From-SVN: r72209

1 files changed, 76 insertions, 91 deletions

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index d6183b8..af31de5 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -544,149 +544,134 @@ rs6000_override_options (const char *default_cpu)
   /* Simplify the entries below by making a mask for any POWER
      variant and any PowerPC variant.  */
 
-  enum {
-    POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
-    POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
-    POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT 
-		     | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC),
-    POWERPC_OPT_MASKS = MASK_PPC_GPOPT | MASK_PPC_GFXOPT | MASK_ALTIVEC,
-    
-    SET_MASKS = (POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT)
-  };
-
-  /* FIXME: In this table, there are a few places where SET_MASKS is
-     used with MASK_POWERPC64 masked off; these indicate processors
-     that are 64-bit but that don't yet have 64-bit switched on by
-     default because it doesn't work in the rest of the backend.
-     There are also some places that SET_MASKS is used with other
-     flags, those are because earlier versions of this table didn't
-     specifically set or clear those flags and I didn't know what the
-     processor supported.  Please delete this comment when all of those
-     cases are gone.  */
+#define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING)
+#define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \
+		       | MASK_PPC_GFXOPT | MASK_POWERPC64)
+#define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT)
 
   static struct ptt
     {
       const char *const name;		/* Canonical processor name.  */
       const enum processor_type processor; /* Processor type enum value.  */
       const int target_enable;	/* Target flags to enable.  */
-      const int target_set;	/* Target flags to change.  */
+      const int target_disable;	/* Target flags to disable.  */
     } const processor_target_table[]
       = {{"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS,
-	    SET_MASKS},
+	    POWER_MASKS | POWERPC_MASKS},
 	 {"power", PROCESSOR_POWER,
 	    MASK_POWER | MASK_MULTIPLE | MASK_STRING,
-	    SET_MASKS},
+	    MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
 	 {"power2", PROCESSOR_POWER,
 	    MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
-	    SET_MASKS},
+	    POWERPC_MASKS | MASK_NEW_MNEMONICS},
 	 {"power3", PROCESSOR_PPC630,
-	    POWERPC_BASE_MASK | MASK_PPC_GFXOPT,
-	    SET_MASKS & ~MASK_POWERPC64 & ~MASK_PPC_GPOPT},
+	    MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
+	    POWER_MASKS},
 	 {"power4", PROCESSOR_POWER4,
-            POWERPC_BASE_MASK | MASK_PPC_GFXOPT,
-	    SET_MASKS & ~MASK_POWERPC64 & ~MASK_PPC_GPOPT},
+            MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
+            POWER_MASKS},
 	 {"powerpc", PROCESSOR_POWERPC,
-	    POWERPC_BASE_MASK,
-	    SET_MASKS},
+	    MASK_POWERPC | MASK_NEW_MNEMONICS,
+	    POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
 	 {"powerpc64", PROCESSOR_POWERPC64,
-	    POWERPC_BASE_MASK | MASK_POWERPC64,
-	    SET_MASKS},
+	    MASK_POWERPC | MASK_POWERPC64 | MASK_NEW_MNEMONICS,
+	    POWER_MASKS | POWERPC_OPT_MASKS},
 	 {"rios", PROCESSOR_RIOS1,
 	    MASK_POWER | MASK_MULTIPLE | MASK_STRING,
-	    SET_MASKS},
+	    MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
 	 {"rios1", PROCESSOR_RIOS1,
 	    MASK_POWER | MASK_MULTIPLE | MASK_STRING,
-	    SET_MASKS},
+	    MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
 	 {"rsc", PROCESSOR_PPC601,
 	    MASK_POWER | MASK_MULTIPLE | MASK_STRING,
-	    SET_MASKS},
+	    MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
 	 {"rsc1", PROCESSOR_PPC601,
 	    MASK_POWER | MASK_MULTIPLE | MASK_STRING,
-	    SET_MASKS},
+	    MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
 	 {"rios2", PROCESSOR_RIOS2,
 	    MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2,
-	    SET_MASKS},
+	    POWERPC_MASKS | MASK_NEW_MNEMONICS},
 	 {"rs64a", PROCESSOR_RS64A,
-	    POWERPC_BASE_MASK,
-	    SET_MASKS},
+	    MASK_POWERPC | MASK_NEW_MNEMONICS,
+	    POWER_MASKS | POWERPC_OPT_MASKS},
 	 {"401", PROCESSOR_PPC403,
-	    POWERPC_BASE_MASK | MASK_SOFT_FLOAT,
-	    SET_MASKS},
+	    MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
+	    POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
 	 {"403", PROCESSOR_PPC403,
-	    POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN,
-	    SET_MASKS},
+	    MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN,
+	    POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
 	 {"405", PROCESSOR_PPC405,
-	    POWERPC_BASE_MASK | MASK_SOFT_FLOAT,
-	    SET_MASKS},
+	    MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
+	    POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
 	 {"405fp", PROCESSOR_PPC405,
-	    POWERPC_BASE_MASK,
-	    SET_MASKS},
+	    MASK_POWERPC | MASK_NEW_MNEMONICS,
+	    POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
 	 {"440", PROCESSOR_PPC440,
-	    POWERPC_BASE_MASK | MASK_SOFT_FLOAT,
-	    SET_MASKS},
+	    MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
+	    POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
 	 {"440fp", PROCESSOR_PPC440,
-	    POWERPC_BASE_MASK,
-	    SET_MASKS},
+	    MASK_POWERPC | MASK_NEW_MNEMONICS,
+	    POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
 	 {"505", PROCESSOR_MPCCORE,
-	    POWERPC_BASE_MASK,
-	    SET_MASKS},
+	    MASK_POWERPC | MASK_NEW_MNEMONICS,
+	    POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
 	 {"601", PROCESSOR_PPC601,
-	    MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING,
-	    SET_MASKS},
+	    MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING,
+	    MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64},
 	 {"602", PROCESSOR_PPC603,
-	    POWERPC_BASE_MASK | MASK_PPC_GFXOPT,
-	    SET_MASKS},
+	    MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
+	    POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
 	 {"603", PROCESSOR_PPC603,
-	    POWERPC_BASE_MASK | MASK_PPC_GFXOPT,
-	    SET_MASKS},
+	    MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
+	    POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
 	 {"603e", PROCESSOR_PPC603,
-	    POWERPC_BASE_MASK | MASK_PPC_GFXOPT,
-	    SET_MASKS},
+	    MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
+	    POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
 	 {"ec603e", PROCESSOR_PPC603,
-	    POWERPC_BASE_MASK | MASK_SOFT_FLOAT,
-	    SET_MASKS},
+	    MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
+	    POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
 	 {"604", PROCESSOR_PPC604,
-	    POWERPC_BASE_MASK | MASK_PPC_GFXOPT,
-	    SET_MASKS},
+	    MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
+	    POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
 	 {"604e", PROCESSOR_PPC604e,
-	    POWERPC_BASE_MASK | MASK_PPC_GFXOPT,
-	    SET_MASKS},
+	    MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
+	    POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
 	 {"620", PROCESSOR_PPC620,
-	    POWERPC_BASE_MASK | MASK_PPC_GFXOPT,
-	    SET_MASKS & ~MASK_POWERPC64 & ~MASK_PPC_GPOPT},
+	    MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
+	    POWER_MASKS},
 	 {"630", PROCESSOR_PPC630,
-	    POWERPC_BASE_MASK | MASK_PPC_GFXOPT,
-	    SET_MASKS & ~MASK_POWERPC64 & ~MASK_PPC_GPOPT},
+	    MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
+	    POWER_MASKS},
 	 {"740", PROCESSOR_PPC750,
- 	    POWERPC_BASE_MASK | MASK_PPC_GFXOPT,
- 	    SET_MASKS},
+ 	    MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
+ 	    POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
 	 {"750", PROCESSOR_PPC750,
- 	    POWERPC_BASE_MASK | MASK_PPC_GFXOPT,
- 	    SET_MASKS},
+ 	    MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
+ 	    POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
 	 {"7400", PROCESSOR_PPC7400,
-            POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC,
-            SET_MASKS},
+            MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
+            POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
 	 {"7450", PROCESSOR_PPC7450,
-            POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC,
-            SET_MASKS},
+            MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
+            POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
 	 {"8540", PROCESSOR_PPC8540,
-	    POWERPC_BASE_MASK | MASK_PPC_GFXOPT,
-	    SET_MASKS},
+	    MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
+	    POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
 	 {"801", PROCESSOR_MPCCORE,
-	    POWERPC_BASE_MASK | MASK_SOFT_FLOAT,
-	    SET_MASKS},
+	    MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
+	    POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
 	 {"821", PROCESSOR_MPCCORE,
-	    POWERPC_BASE_MASK | MASK_SOFT_FLOAT,
-	    SET_MASKS},
+	    MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
+	    POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
 	 {"823", PROCESSOR_MPCCORE,
-	    POWERPC_BASE_MASK | MASK_SOFT_FLOAT,
-	    SET_MASKS},
+	    MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
+	    POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
 	 {"860", PROCESSOR_MPCCORE,
-	    POWERPC_BASE_MASK | MASK_SOFT_FLOAT,
-	    SET_MASKS},
+	    MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
+	    POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
 	 {"970", PROCESSOR_POWER4,
-	    POWERPC_BASE_MASK | POWERPC_OPT_MASKS | MASK_ALTIVEC,
-	    SET_MASKS & ~MASK_POWERPC64}};
+	    MASK_POWERPC | POWERPC_OPT_MASKS | MASK_NEW_MNEMONICS,
+	    POWER_MASKS}};
 
   const size_t ptt_size = ARRAY_SIZE (processor_target_table);
 
@@ -712,8 +697,8 @@ rs6000_override_options (const char *default_cpu)
 
 		if (ptr->set_arch_p)
 		  {
-		    target_flags &= ~processor_target_table[j].target_set;
 		    target_flags |= processor_target_table[j].target_enable;
+		    target_flags &= ~processor_target_table[j].target_disable;
 		  }
 		break;
 	      }