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author | Greta Yorsh <greta.yorsh@arm.com> | 2013-04-19 14:25:09 +0100 |
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committer | Greta Yorsh <gretay@gcc.gnu.org> | 2013-04-19 14:25:09 +0100 |
commit | ede22fc330f055810555d867de5a8e3d3f94ad63 (patch) | |
tree | 390726a9634869b4409170e1d03df1c3bd276dff /gcc | |
parent | 67bc84fbb05664ec45d2a0319520c96f011a9596 (diff) | |
download | gcc-ede22fc330f055810555d867de5a8e3d3f94ad63.zip gcc-ede22fc330f055810555d867de5a8e3d3f94ad63.tar.gz gcc-ede22fc330f055810555d867de5a8e3d3f94ad63.tar.bz2 |
arm.c (load_multiple_sequence, [...]): Fix spelling in two comments.
2013-04-19 Greta Yorsh <Greta.Yorsh@arm.com>
* config/arm/arm.c (load_multiple_sequence, ldm_stm_operation_p): Fix
spelling in two comments.
From-SVN: r198093
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/ChangeLog | 5 | ||||
-rw-r--r-- | gcc/config/arm/arm.c | 4 |
2 files changed, 7 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 439471d..e395bd1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2013-04-19 Greta Yorsh <Greta.Yorsh@arm.com> + * config/arm/arm.c (load_multiple_sequence, ldm_stm_operation_p): Fix + spelling in two comments. + +2013-04-19 Greta Yorsh <Greta.Yorsh@arm.com> + PR target/56797 * config/arm/arm.c (load_multiple_sequence): Require SP as base register for loads if SP is in the register list. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 7567afc..464d91c 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -10491,7 +10491,7 @@ ldm_stm_operation_p (rtx op, bool load, enum machine_mode mode, /* Don't allow SP to be loaded unless it is also the base register. It guarantees that SP is reset correctly when an LDM instruction - is interruptted. Otherwise, we might end up with a corrupt stack. */ + is interrupted. Otherwise, we might end up with a corrupt stack. */ if (load && (REGNO (reg) == SP_REGNUM) && (REGNO (addr) != SP_REGNUM)) return false; @@ -10757,7 +10757,7 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order, /* Don't allow SP to be loaded unless it is also the base register. It guarantees that SP is reset correctly when - an LDM instruction is interruptted. Otherwise, we might + an LDM instruction is interrupted. Otherwise, we might end up with a corrupt stack. */ if (unsorted_regs[i] == SP_REGNUM && base_reg != SP_REGNUM) return 0; |