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| author | Andrew Pinski <pinskia@physics.uc.edu> | 2004-04-29 20:23:36 +0000 |
|---|---|---|
| committer | Andrew Pinski <pinskia@gcc.gnu.org> | 2004-04-29 13:23:36 -0700 |
| commit | ec52e7d58f8062c91b7698ff9ce11bc5ddb8f3fc (patch) | |
| tree | 6ef0a8478f744de71cf03dbbeeef24247d3054e6 /gcc | |
| parent | 15a6f2c33e043df5c299ad9061ee2e87f58e1def (diff) | |
| download | gcc-ec52e7d58f8062c91b7698ff9ce11bc5ddb8f3fc.zip gcc-ec52e7d58f8062c91b7698ff9ce11bc5ddb8f3fc.tar.gz gcc-ec52e7d58f8062c91b7698ff9ce11bc5ddb8f3fc.tar.bz2 | |
rs6000-power2-1.c: Change the options to be more correct.
2004-04-29 Andrew Pinski <pinskia@physics.uc.edu>
* gcc.dg/rs6000-power2-1.c: Change the options to be more correct.
* gcc.dg/rs6000-power2-2.c: Change the options to be more correct.
Change the asm registers to be in form of frN instead of fN.
From-SVN: r81303
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.dg/rs6000-power2-1.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.dg/rs6000-power2-2.c | 8 |
3 files changed, 11 insertions, 5 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 718a92e..2214658 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2004-04-29 Andrew Pinski <pinskia@physics.uc.edu> + + * gcc.dg/rs6000-power2-1.c: Change the options to be more correct. + * gcc.dg/rs6000-power2-2.c: Change the options to be more correct. + Change the asm registers to be in form of frN instead of fN. + 2004-04-28 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> * gcc.dg/torture/builtin-convert-2.c: New test. diff --git a/gcc/testsuite/gcc.dg/rs6000-power2-1.c b/gcc/testsuite/gcc.dg/rs6000-power2-1.c index 7f22b98..0e9b5aa 100644 --- a/gcc/testsuite/gcc.dg/rs6000-power2-1.c +++ b/gcc/testsuite/gcc.dg/rs6000-power2-1.c @@ -1,5 +1,5 @@ /* { dg-do assemble { target powerpc-*-* rs6000-*-* } } */ -/* { dg-options "-O -mpower2 -fno-schedule-insns -w" } */ +/* { dg-options "-O3 -mcpu=power2 -fno-schedule-insns -w -mhard-float" } */ /* This used to ICE as the peephole was not checking to see if the register is a floating point one (I think this cannot happen in real life except in this example). */ diff --git a/gcc/testsuite/gcc.dg/rs6000-power2-2.c b/gcc/testsuite/gcc.dg/rs6000-power2-2.c index dda4852..74cc0ec 100644 --- a/gcc/testsuite/gcc.dg/rs6000-power2-2.c +++ b/gcc/testsuite/gcc.dg/rs6000-power2-2.c @@ -1,13 +1,13 @@ /* { dg-do assemble { target powerpc-*-* rs6000-*-* } } */ -/* { dg-options "-O -mpower2 -fno-schedule-insns" } */ +/* { dg-options "-O3 -mcpu=power2 -fno-schedule-insns -w -mhard-float" } */ /* { dg-final { scan-assembler-not "lfd" } } */ /* { dg-final { scan-assembler-not "sfd" } } */ /* { dg-final { scan-assembler "lfq" } } */ /* { dg-final { scan-assembler "sfq" } } */ -register double t1 __asm__("f0"); -register double t2 __asm__("f1"); -register double t3 __asm__("f2"), t4 __asm__("f3"); +register double t1 __asm__("fr0"); +register double t2 __asm__("fr1"); +register double t3 __asm__("fr2"), t4 __asm__("fr3"); void t(double *a, double *b) { t1 = a[-1]; |