sparc.c (load_pic_register): Emit the appropriate variant of the load_pcrel_sym pattern.

	* config/sparc/sparc.c (load_pic_register): Emit the appropriate
	variant of the load_pcrel_sym pattern.
	* config/sparc/sparc.md (P macro): Move to the top.
	(load_pcrel_sym): Macroize using P.
	(save_register_window): Likewise.

From-SVN: r93859

3 files changed, 27 insertions, 26 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 08cdcc5..a8c2a0a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2005-01-18  Eric Botcazou  <ebotcazou@libertysurf.fr>
+
+	* config/sparc/sparc.c (load_pic_register): Emit the appropriate
+	variant of the load_pcrel_sym pattern.
+	* config/sparc/sparc.md (P macro): Move to the top.
+	(load_pcrel_sym): Macroize using P.
+	(save_register_window): Likewise.
+
 2005-01-18  Aldy Hernandez  <aldyh@redhat.com>
 
 	* config/rs6000/rs6000.md ("sunordered"): Disable for e500.
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 04547a0..43aa2f1 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -3981,8 +3981,12 @@ load_pic_register (void)
   add_pc_to_pic_symbol = gen_rtx_SYMBOL_REF (Pmode, add_pc_to_pic_symbol_name);
 
   flag_pic = 0;
-  emit_insn (gen_load_pcrel_sym (pic_offset_table_rtx, global_offset_table,
-				 add_pc_to_pic_symbol));
+  if (TARGET_ARCH64)
+    emit_insn (gen_load_pcrel_symdi (pic_offset_table_rtx, global_offset_table,
+				     add_pc_to_pic_symbol));
+  else
+    emit_insn (gen_load_pcrel_symsi (pic_offset_table_rtx, global_offset_table,
+				     add_pc_to_pic_symbol));
   flag_pic = orig_flag_pic;
 
   /* Need to emit this whether or not we obey regdecls,
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 34839be..6153b5a 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -68,6 +68,8 @@
    (UNSPECV_SAVEW		6)
   ])
 
+(define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
+
 ;; The upper 32 fp regs on the v9 can't hold SFmode values.  To deal with this
 ;; a second register class, EXTRA_FP_REGS, exists for the v9 chip.  The name
 ;; is a bit of a misnomer as it covers all 64 fp regs.  The corresponding
@@ -1694,11 +1696,11 @@
 ;; value subject to a PC-relative relocation.  Operand 2 is a helper function
 ;; that adds the PC value at the call point to operand 0.
 
-(define_insn "load_pcrel_sym"
-  [(set (match_operand 0 "register_operand" "=r")
-	(unspec [(match_operand 1 "symbolic_operand" "")
-		 (match_operand 2 "call_operand_address" "")] UNSPEC_LOAD_PCREL_SYM))
-   (clobber (reg:SI 15))]
+(define_insn "load_pcrel_sym<P:mode>"
+  [(set (match_operand:P 0 "register_operand" "=r")
+	(unspec:P [(match_operand:P 1 "symbolic_operand" "")
+		   (match_operand:P 2 "call_operand_address" "")] UNSPEC_LOAD_PCREL_SYM))
+   (clobber (reg:P 15))]
   ""
 {
   if (flag_delayed_branch)
@@ -7721,23 +7723,12 @@
 ;;  (set (%sp) (unspec_volatile [(%sp) (-frame_size)] UNSPECV_SAVEW))
 ;;  (set (%i7) (%o7))]
 
-(define_insn "save_register_windowdi"
-  [(set (reg:DI 30) (reg:DI 14))
-   (set (reg:DI 14) (unspec_volatile:DI [(reg:DI 14)
-					 (match_operand:DI 0 "arith_operand" "rI")]
-				        UNSPECV_SAVEW))
-   (set (reg:DI 31) (reg:DI 15))]
-  "TARGET_ARCH64"
-  "save\t%%sp, %0, %%sp"
-  [(set_attr "type" "savew")])
-
-(define_insn "save_register_windowsi"
-  [(set (reg:SI 30) (reg:SI 14))
-   (set (reg:SI 14) (unspec_volatile:SI [(reg:SI 14)
-					 (match_operand:SI 0 "arith_operand" "rI")]
-				        UNSPECV_SAVEW))
-   (set (reg:SI 31) (reg:SI 15))]
-  "!TARGET_ARCH64"
+(define_insn "save_register_window<P:mode>"
+  [(set (reg:P 30) (reg:P 14))
+   (set (reg:P 14) (unspec_volatile:P [(reg:P 14)
+				       (match_operand:P 0 "arith_operand" "rI")] UNSPECV_SAVEW))
+   (set (reg:P 31) (reg:P 15))]
+  ""
   "save\t%%sp, %0, %%sp"
   [(set_attr "type" "savew")])
 
@@ -9103,8 +9094,6 @@
   [(set_attr "type" "fga")
    (set_attr "fptype" "double")])
 
-(define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
-
 (define_insn "alignaddr<P:mode>_vis"
   [(set (match_operand:P 0 "register_operand" "=r")
         (unspec:P [(match_operand:P 1 "reg_or_0_operand" "rJ")