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| author | Andrew Stubbs <ams@codesourcery.com> | 2019-12-03 16:20:29 +0000 |
|---|---|---|
| committer | Andrew Stubbs <ams@gcc.gnu.org> | 2019-12-03 16:20:29 +0000 |
| commit | e93b5262fdec906660ce7b7763d0e76e705f0803 (patch) | |
| tree | bad1894f714327d8759bf9a002be31b132408c23 /gcc | |
| parent | 43aae289866f5ea55d187444520412554aa2e171 (diff) | |
| download | gcc-e93b5262fdec906660ce7b7763d0e76e705f0803.zip gcc-e93b5262fdec906660ce7b7763d0e76e705f0803.tar.gz gcc-e93b5262fdec906660ce7b7763d0e76e705f0803.tar.bz2 | |
Add missing amdgcn vcondu patterns
2019-12-03 Andrew Stubbs <ams@codesourcery.com>
gcc/
* config/gcn/gcn-valu.md: Change "vcondu" patterns to use VEC_1REG_MODE
for the data mode.
From-SVN: r278940
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/gcn/gcn-valu.md | 20 |
2 files changed, 15 insertions, 10 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9efc808..2902cdc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2019-12-03 Andrew Stubbs <ams@codesourcery.com> + + * config/gcn/gcn-valu.md: Change "vcondu" patterns to use VEC_1REG_MODE + for the data mode. + 2019-12-03 Richard Biener <rguenther@suse.de> PR tree-optimization/92758 diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index 66b8229..f3262e2 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -2596,10 +2596,10 @@ DONE; }) -(define_expand "vcondu<VEC_1REG_INT_MODE:mode><VEC_1REG_INT_ALT:mode>" - [(match_operand:VEC_1REG_INT_MODE 0 "register_operand") - (match_operand:VEC_1REG_INT_MODE 1 "gcn_vop3_operand") - (match_operand:VEC_1REG_INT_MODE 2 "gcn_alu_operand") +(define_expand "vcondu<VEC_1REG_MODE:mode><VEC_1REG_INT_ALT:mode>" + [(match_operand:VEC_1REG_MODE 0 "register_operand") + (match_operand:VEC_1REG_MODE 1 "gcn_vop3_operand") + (match_operand:VEC_1REG_MODE 2 "gcn_alu_operand") (match_operator 3 "comparison_operator" [(match_operand:VEC_1REG_INT_ALT 4 "gcn_alu_operand") (match_operand:VEC_1REG_INT_ALT 5 "gcn_vop3_operand")])] @@ -2608,15 +2608,15 @@ rtx tmp = gen_reg_rtx (DImode); emit_insn (gen_vec_cmp<VEC_1REG_INT_ALT:mode>di (tmp, operands[3], operands[4], operands[5])); - emit_insn (gen_vcond_mask_<VEC_1REG_INT_MODE:mode>di + emit_insn (gen_vcond_mask_<VEC_1REG_MODE:mode>di (operands[0], operands[1], operands[2], tmp)); DONE; }) -(define_expand "vcondu<VEC_1REG_INT_MODE:mode><VEC_1REG_INT_ALT:mode>_exec" - [(match_operand:VEC_1REG_INT_MODE 0 "register_operand") - (match_operand:VEC_1REG_INT_MODE 1 "gcn_vop3_operand") - (match_operand:VEC_1REG_INT_MODE 2 "gcn_alu_operand") +(define_expand "vcondu<VEC_1REG_MODE:mode><VEC_1REG_INT_ALT:mode>_exec" + [(match_operand:VEC_1REG_MODE 0 "register_operand") + (match_operand:VEC_1REG_MODE 1 "gcn_vop3_operand") + (match_operand:VEC_1REG_MODE 2 "gcn_alu_operand") (match_operator 3 "comparison_operator" [(match_operand:VEC_1REG_INT_ALT 4 "gcn_alu_operand") (match_operand:VEC_1REG_INT_ALT 5 "gcn_vop3_operand")]) @@ -2626,7 +2626,7 @@ rtx tmp = gen_reg_rtx (DImode); emit_insn (gen_vec_cmp<VEC_1REG_INT_ALT:mode>di_exec (tmp, operands[3], operands[4], operands[5], operands[6])); - emit_insn (gen_vcond_mask_<VEC_1REG_INT_MODE:mode>di + emit_insn (gen_vcond_mask_<VEC_1REG_MODE:mode>di (operands[0], operands[1], operands[2], tmp)); DONE; }) |