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| author | H.J. Lu <hjl.tools@gmail.com> | 2022-03-21 11:45:59 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2022-03-21 15:34:36 -0700 |
| commit | e8b6afa98f0a390c955a089a3d61fdd24f4e1d3a (patch) | |
| tree | 254268e8936d874b44f81c218127455f0e71d1e8 /gcc | |
| parent | c65bd532e225996cc9c5b75355d2cb648d0bcfc5 (diff) | |
| download | gcc-e8b6afa98f0a390c955a089a3d61fdd24f4e1d3a.zip gcc-e8b6afa98f0a390c955a089a3d61fdd24f4e1d3a.tar.gz gcc-e8b6afa98f0a390c955a089a3d61fdd24f4e1d3a.tar.bz2 | |
x86: Disable SSE in ISA2 for -mgeneral-regs-only
Replace OPTION_MASK_ISA2_AVX512F_UNSET with OPTION_MASK_ISA2_SSE_UNSET
in OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET to disable SSE, AVX and
AVX512 ISAs.
gcc/
PR target/105000
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET): Replace
OPTION_MASK_ISA2_AVX512F_UNSET with OPTION_MASK_ISA2_SSE_UNSET.
gcc/testsuite/
PR target/105000
* gcc.target/i386/pr105000-1.c: New test.
* gcc.target/i386/pr105000-2.c: Likewise.
* gcc.target/i386/pr105000-3.c: Likewise.
* gcc.target/i386/pr105000-4.c: Likewise.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/common/config/i386/i386-common.cc | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr105000-1.c | 11 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr105000-2.c | 11 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr105000-3.c | 11 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr105000-4.c | 11 |
5 files changed, 45 insertions, 1 deletions
diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index 449df63..07fdd04 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -321,7 +321,7 @@ along with GCC; see the file COPYING3. If not see | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET \ | OPTION_MASK_ISA2_AVX512FP16_UNSET) #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \ - (OPTION_MASK_ISA2_AVX512F_UNSET) + OPTION_MASK_ISA2_SSE_UNSET #define OPTION_MASK_ISA2_AVX_UNSET OPTION_MASK_ISA2_AVX2_UNSET #define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET #define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET diff --git a/gcc/testsuite/gcc.target/i386/pr105000-1.c b/gcc/testsuite/gcc.target/i386/pr105000-1.c new file mode 100644 index 0000000..020e2ad --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr105000-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mshstk -mavxvnni" } */ + +#include <x86gprintrin.h> + +__attribute__((target("no-mmx,no-sse"))) +int +foo () +{ + return _get_ssp (); +} diff --git a/gcc/testsuite/gcc.target/i386/pr105000-2.c b/gcc/testsuite/gcc.target/i386/pr105000-2.c new file mode 100644 index 0000000..a113fd1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr105000-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mshstk -mkl" } */ + +#include <x86gprintrin.h> + +__attribute__((target("no-mmx,no-sse"))) +int +foo () +{ + return _get_ssp (); +} diff --git a/gcc/testsuite/gcc.target/i386/pr105000-3.c b/gcc/testsuite/gcc.target/i386/pr105000-3.c new file mode 100644 index 0000000..7e82925 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr105000-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mshstk -mwidekl" } */ + +#include <x86gprintrin.h> + +__attribute__((target("no-mmx,no-sse"))) +int +foo () +{ + return _get_ssp (); +} diff --git a/gcc/testsuite/gcc.target/i386/pr105000-4.c b/gcc/testsuite/gcc.target/i386/pr105000-4.c new file mode 100644 index 0000000..195eabe --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr105000-4.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mshstk -mavx512fp16" } */ + +#include <x86gprintrin.h> + +__attribute__((target("no-mmx,no-sse"))) +int +foo () +{ + return _get_ssp (); +} |