i386.c (override_options): Revert 2004-11-24 change.

	* config/i386/i386.c (override_options): Revert 2004-11-24 change.
	* config/i386/i386.md (fmodsf3, dremsf3, *sinsf2, *cossf2, sincossf3,
	*tansf3_1, tansf2, atan2sf3_1, atan2sf3, atansf2, asinsf2, acossf2,
	logsf2, log10sf2, log2sf2, log1psf2, logbsf2, ilogbsf2, expsf2,
	exp10sf2, exp2sf2, expm1sf2, rintsf2, floorsf2, ceilsf2, btruncsf2,
	nearbyintsf2): Disable for TARGET_SSE_MATH.  Leave patterns enabled
	for TARGET_MIX_SSE_I387.
	(fmoddf3, dremdf3, *sindf2, *sinextendsfdf2, *cosdf2, *cosextendsfdf2,
	sincosdf3, *sincosextendsfdf3, *tandf3_1, tandf2, atan2df3_1,
	atan2df3, atandf2, asindf2, acosdf2, logdf2, log10df2, log2df2,
	log1pdf2, logbdf2, expdf2, exp10df2, exp2df2, expm1df2, rintdf2,
	floordf2, ceildf2, btruncdf2, nearbyintdf2): Disable for
	(TARGET_SSE2 && TARGET_SSE_MATH).  Leave patterns enabled for
	TARGET_MIX_SSE_I387.
	(atan2sf3, atan2df3, atan2xf3): Remove register constraints
	from expander.

From-SVN: r93815

3 files changed, 84 insertions, 13 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8e63550..141cbc4 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,24 @@
 2005-01-18  Uros Bizjak  <uros@kss-loka.si>
 
+	* config/i386/i386.c (override_options): Revert 2004-11-24 change.
+	* config/i386/i386.md (fmodsf3, dremsf3, *sinsf2, *cossf2, sincossf3,
+	*tansf3_1, tansf2, atan2sf3_1, atan2sf3, atansf2, asinsf2, acossf2,
+	logsf2, log10sf2, log2sf2, log1psf2, logbsf2, ilogbsf2, expsf2,
+	exp10sf2, exp2sf2, expm1sf2, rintsf2, floorsf2, ceilsf2, btruncsf2,
+	nearbyintsf2): Disable for TARGET_SSE_MATH.  Leave patterns enabled
+	for TARGET_MIX_SSE_I387.
+	(fmoddf3, dremdf3, *sindf2, *sinextendsfdf2, *cosdf2, *cosextendsfdf2,
+	sincosdf3, *sincosextendsfdf3, *tandf3_1, tandf2, atan2df3_1,
+	atan2df3, atandf2, asindf2, acosdf2, logdf2, log10df2, log2df2,
+	log1pdf2, logbdf2, expdf2, exp10df2, exp2df2, expm1df2, rintdf2,
+	floordf2, ceildf2, btruncdf2, nearbyintdf2): Disable for
+	(TARGET_SSE2 && TARGET_SSE_MATH).  Leave patterns enabled for
+	TARGET_MIX_SSE_I387.
+	(atan2sf3, atan2df3, atan2xf3): Remove register constraints
+	from expander.
+
+2005-01-18  Uros Bizjak  <uros@kss-loka.si>
+
 	PR target/19424
 	* config/i386/mmx.md (*movv2sf_internal_rex64, *movv2sf_internal):
 	Add movaps alternative for xmm reg->reg move.
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 4bc0c75..5f00e4a 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -1557,10 +1557,6 @@ override_options (void)
 	error ("bad value (%s) for -mfpmath= switch", ix86_fpmath_string);
     }
 
-  /* If fpmath doesn't include 387, disable use of x87 intrinsics.  */
-  if (! (ix86_fpmath & FPMATH_387))
-    target_flags |= MASK_NO_FANCY_MATH_387;
-
   if ((x86_accumulate_outgoing_args & TUNEMASK)
       && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
       && !optimize_size)
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 674d0935..949c392 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -14766,6 +14766,7 @@
    (use (match_operand:SF 1 "register_operand" ""))
    (use (match_operand:SF 2 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
+   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx label = gen_label_rtx ();
@@ -14790,6 +14791,7 @@
    (use (match_operand:DF 1 "register_operand" ""))
    (use (match_operand:DF 2 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx label = gen_label_rtx ();
@@ -14849,6 +14851,7 @@
    (use (match_operand:SF 1 "register_operand" ""))
    (use (match_operand:SF 2 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
+   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx label = gen_label_rtx ();
@@ -14873,6 +14876,7 @@
    (use (match_operand:DF 1 "register_operand" ""))
    (use (match_operand:DF 2 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx label = gen_label_rtx ();
@@ -14915,6 +14919,7 @@
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
   "fsin"
   [(set_attr "type" "fpspc")
@@ -14924,6 +14929,7 @@
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))]
   "TARGET_USE_FANCY_MATH_387
+   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
   "fsin"
   [(set_attr "type" "fpspc")
@@ -14935,6 +14941,7 @@
 		     (match_operand:SF 1 "register_operand" "0"))]
 		   UNSPEC_SIN))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
   "fsin"
   [(set_attr "type" "fpspc")
@@ -14953,6 +14960,7 @@
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
   "fcos"
   [(set_attr "type" "fpspc")
@@ -14962,6 +14970,7 @@
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))]
   "TARGET_USE_FANCY_MATH_387
+   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
   "fcos"
   [(set_attr "type" "fpspc")
@@ -14973,6 +14982,7 @@
 		     (match_operand:SF 1 "register_operand" "0"))]
 		   UNSPEC_COS))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
   "fcos"
   [(set_attr "type" "fpspc")
@@ -15000,6 +15010,7 @@
    (set (match_operand:DF 1 "register_operand" "=u")
         (unspec:DF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
   "fsincos"
   [(set_attr "type" "fpspc")
@@ -15034,6 +15045,7 @@
    (set (match_operand:SF 1 "register_operand" "=u")
         (unspec:SF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
   "TARGET_USE_FANCY_MATH_387
+   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
   "fsincos"
   [(set_attr "type" "fpspc")
@@ -15070,6 +15082,7 @@
         (unspec:DF [(float_extend:DF
 		     (match_dup 2))] UNSPEC_SINCOS_SIN))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
   "fsincos"
   [(set_attr "type" "fpspc")
@@ -15144,6 +15157,7 @@
    (set (match_operand:DF 1 "register_operand" "=u")
         (unspec:DF [(match_dup 2)] UNSPEC_TAN_TAN))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
   "fptan"
   [(set_attr "type" "fpspc")
@@ -15174,6 +15188,7 @@
 	      (set (match_operand:DF 0 "register_operand" "")
 		   (unspec:DF [(match_dup 1)] UNSPEC_TAN_TAN))])]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   operands[2] = gen_reg_rtx (DFmode);
@@ -15186,6 +15201,7 @@
    (set (match_operand:SF 1 "register_operand" "=u")
         (unspec:SF [(match_dup 2)] UNSPEC_TAN_TAN))]
   "TARGET_USE_FANCY_MATH_387
+   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
   "fptan"
   [(set_attr "type" "fpspc")
@@ -15216,6 +15232,7 @@
 	      (set (match_operand:SF 0 "register_operand" "")
 		   (unspec:SF [(match_dup 1)] UNSPEC_TAN_TAN))])]
   "TARGET_USE_FANCY_MATH_387
+   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   operands[2] = gen_reg_rtx (SFmode);
@@ -15270,16 +15287,18 @@
 		   UNSPEC_FPATAN))
    (clobber (match_scratch:DF 3 "=1"))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
   "fpatan"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "DF")])
 
 (define_expand "atan2df3"
-  [(use (match_operand:DF 0 "register_operand" "=f"))
-   (use (match_operand:DF 2 "register_operand" "0"))
-   (use (match_operand:DF 1 "register_operand" "u"))]
+  [(use (match_operand:DF 0 "register_operand" ""))
+   (use (match_operand:DF 2 "register_operand" ""))
+   (use (match_operand:DF 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx copy = gen_reg_rtx (DFmode);
@@ -15295,6 +15314,7 @@
 		    UNSPEC_FPATAN))
 	      (clobber (match_scratch:DF 3 ""))])]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   operands[2] = gen_reg_rtx (DFmode);
@@ -15308,16 +15328,18 @@
 		   UNSPEC_FPATAN))
    (clobber (match_scratch:SF 3 "=1"))]
   "TARGET_USE_FANCY_MATH_387
+   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
   "fpatan"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "SF")])
 
 (define_expand "atan2sf3"
-  [(use (match_operand:SF 0 "register_operand" "=f"))
-   (use (match_operand:SF 2 "register_operand" "0"))
-   (use (match_operand:SF 1 "register_operand" "u"))]
+  [(use (match_operand:SF 0 "register_operand" ""))
+   (use (match_operand:SF 2 "register_operand" ""))
+   (use (match_operand:SF 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
+   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx copy = gen_reg_rtx (SFmode);
@@ -15333,6 +15355,7 @@
 		    UNSPEC_FPATAN))
 	      (clobber (match_scratch:SF 3 ""))])]
   "TARGET_USE_FANCY_MATH_387
+   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   operands[2] = gen_reg_rtx (SFmode);
@@ -15352,9 +15375,9 @@
    (set_attr "mode" "XF")])
 
 (define_expand "atan2xf3"
-  [(use (match_operand:XF 0 "register_operand" "=f"))
-   (use (match_operand:XF 2 "register_operand" "0"))
-   (use (match_operand:XF 1 "register_operand" "u"))]
+  [(use (match_operand:XF 0 "register_operand" ""))
+   (use (match_operand:XF 2 "register_operand" ""))
+   (use (match_operand:XF 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
    && flag_unsafe_math_optimizations"
 {
@@ -15390,6 +15413,7 @@
    (set (match_operand:DF 0 "register_operand" "")
 	(float_truncate:DF (match_dup 7)))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   int i;
@@ -15413,6 +15437,7 @@
    (set (match_operand:SF 0 "register_operand" "")
 	(float_truncate:SF (match_dup 7)))]
   "TARGET_USE_FANCY_MATH_387
+   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   int i;
@@ -15457,6 +15482,7 @@
    (set (match_operand:DF 0 "register_operand" "")
 	(float_truncate:DF (match_dup 7)))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   int i;
@@ -15480,6 +15506,7 @@
    (set (match_operand:SF 0 "register_operand" "")
 	(float_truncate:SF (match_dup 7)))]
   "TARGET_USE_FANCY_MATH_387
+   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   int i;
@@ -15533,6 +15560,7 @@
    (set (match_operand:SF 0 "register_operand" "")
 	(float_truncate:SF (match_dup 4)))]
   "TARGET_USE_FANCY_MATH_387
+   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx temp;
@@ -15555,6 +15583,7 @@
    (set (match_operand:DF 0 "register_operand" "")
 	(float_truncate:DF (match_dup 4)))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx temp;
@@ -15592,6 +15621,7 @@
    (set (match_operand:SF 0 "register_operand" "")
 	(float_truncate:SF (match_dup 4)))]
   "TARGET_USE_FANCY_MATH_387
+   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx temp;
@@ -15614,6 +15644,7 @@
    (set (match_operand:DF 0 "register_operand" "")
 	(float_truncate:DF (match_dup 4)))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx temp;
@@ -15651,6 +15682,7 @@
    (set (match_operand:SF 0 "register_operand" "")
 	(float_truncate:SF (match_dup 4)))]
   "TARGET_USE_FANCY_MATH_387
+   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   operands[2] = gen_reg_rtx (XFmode);
@@ -15670,6 +15702,7 @@
    (set (match_operand:DF 0 "register_operand" "")
 	(float_truncate:DF (match_dup 4)))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   operands[2] = gen_reg_rtx (XFmode);
@@ -15707,6 +15740,7 @@
   [(use (match_operand:SF 0 "register_operand" ""))
    (use (match_operand:SF 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
+   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx op0 = gen_reg_rtx (XFmode);
@@ -15722,6 +15756,7 @@
   [(use (match_operand:DF 0 "register_operand" ""))
    (use (match_operand:DF 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx op0 = gen_reg_rtx (XFmode);
@@ -15765,6 +15800,7 @@
    (set (match_operand:SF 0 "register_operand" "")
 	(float_truncate:SF (match_dup 4)))]
   "TARGET_USE_FANCY_MATH_387
+   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   operands[2] = gen_reg_rtx (XFmode);
@@ -15782,6 +15818,7 @@
    (set (match_operand:DF 0 "register_operand" "")
 	(float_truncate:DF (match_dup 4)))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   operands[2] = gen_reg_rtx (XFmode);
@@ -15811,6 +15848,7 @@
 	           (fix:SI (match_dup 3)))
 	      (clobber (reg:CC FLAGS_REG))])]
   "TARGET_USE_FANCY_MATH_387
+   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   operands[2] = gen_reg_rtx (XFmode);
@@ -15858,6 +15896,7 @@
    (set (match_operand:SF 0 "register_operand" "")
 	(float_truncate:SF (match_dup 10)))]
   "TARGET_USE_FANCY_MATH_387
+   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx temp;
@@ -15887,6 +15926,7 @@
    (set (match_operand:DF 0 "register_operand" "")
 	(float_truncate:DF (match_dup 10)))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx temp;
@@ -15942,6 +15982,7 @@
    (set (match_operand:SF 0 "register_operand" "")
 	(float_truncate:SF (match_dup 10)))]
   "TARGET_USE_FANCY_MATH_387
+   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx temp;
@@ -15971,6 +16012,7 @@
    (set (match_operand:DF 0 "register_operand" "")
 	(float_truncate:DF (match_dup 10)))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx temp;
@@ -16025,6 +16067,7 @@
    (set (match_operand:SF 0 "register_operand" "")
 	(float_truncate:SF (match_dup 8)))]
   "TARGET_USE_FANCY_MATH_387
+   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   int i;
@@ -16050,6 +16093,7 @@
    (set (match_operand:DF 0 "register_operand" "")
 	(float_truncate:DF (match_dup 8)))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   int i;
@@ -16105,6 +16149,7 @@
    (set (match_operand:DF 0 "register_operand" "")
 	(float_truncate:DF (match_dup 14)))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx temp;
@@ -16141,6 +16186,7 @@
    (set (match_operand:SF 0 "register_operand" "")
 	(float_truncate:SF (match_dup 14)))]
   "TARGET_USE_FANCY_MATH_387
+   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx temp;
@@ -16202,6 +16248,7 @@
   [(use (match_operand:DF 0 "register_operand" ""))
    (use (match_operand:DF 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx op0 = gen_reg_rtx (XFmode);
@@ -16218,6 +16265,7 @@
   [(use (match_operand:SF 0 "register_operand" ""))
    (use (match_operand:SF 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
+   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx op0 = gen_reg_rtx (XFmode);
@@ -16257,6 +16305,7 @@
   [(use (match_operand:DF 0 "register_operand" ""))
    (use (match_operand:DF 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx op0 = gen_reg_rtx (XFmode);
@@ -16277,6 +16326,7 @@
   [(use (match_operand:SF 0 "register_operand" ""))
    (use (match_operand:SF 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
+   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx op0 = gen_reg_rtx (XFmode);
@@ -16325,6 +16375,7 @@
   [(use (match_operand:DF 0 "register_operand" ""))
    (use (match_operand:DF 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx op0 = gen_reg_rtx (XFmode);
@@ -16345,6 +16396,7 @@
   [(use (match_operand:SF 0 "register_operand" ""))
    (use (match_operand:SF 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
+   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx op0 = gen_reg_rtx (XFmode);
@@ -16393,6 +16445,7 @@
   [(use (match_operand:DF 0 "register_operand" ""))
    (use (match_operand:DF 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx op0 = gen_reg_rtx (XFmode);
@@ -16413,6 +16466,7 @@
   [(use (match_operand:SF 0 "register_operand" ""))
    (use (match_operand:SF 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
+   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx op0 = gen_reg_rtx (XFmode);
@@ -16461,6 +16515,7 @@
   [(use (match_operand:DF 0 "register_operand" ""))
    (use (match_operand:DF 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx op0 = gen_reg_rtx (XFmode);
@@ -16481,6 +16536,7 @@
   [(use (match_operand:SF 0 "register_operand" ""))
    (use (match_operand:SF 1 "register_operand" ""))]
   "TARGET_USE_FANCY_MATH_387
+   && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
 {
   rtx op0 = gen_reg_rtx (XFmode);