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| author | Richard Sandiford <rsandifo@redhat.com> | 2001-08-02 10:27:03 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2001-08-02 10:27:03 +0000 |
| commit | d6b6ba29213242c1e0ce9cc9a63a4632e1f01ca2 (patch) | |
| tree | af59f5563126545c7076183dd35919d5728671be /gcc | |
| parent | d3259baad87c1abaf745fc9c1b1d18bf6e26b8ff (diff) | |
| download | gcc-d6b6ba29213242c1e0ce9cc9a63a4632e1f01ca2.zip gcc-d6b6ba29213242c1e0ce9cc9a63a4632e1f01ca2.tar.gz gcc-d6b6ba29213242c1e0ce9cc9a63a4632e1f01ca2.tar.bz2 | |
mips.md (movdicc): Make conditional on TARGET_64BIT.
* mips.md (movdicc): Make conditional on TARGET_64BIT. Likewise
for the unnamed instructions it expands to.
From-SVN: r44568
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 8 |
2 files changed, 9 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 21d54fa..27de1f8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2001-08-02 Richard Sandiford <rsandifo@redhat.com> + + * mips.md (movdicc): Make conditional on TARGET_64BIT. Likewise + for the unnamed instructions it expands to. + 2001-08-02 Richard Henderson <rth@redhat.com> * regclass.c (call_really_used_regs): Conditionally define. diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 58fa963..092e396 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -10180,7 +10180,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\;j\\t%2" (const_int 0)]) (match_operand:DI 2 "se_reg_or_0_operand" "dJ,0") (match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))] - "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE" + "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT" "@ mov%B4\\t%0,%z2,%1 mov%b4\\t%0,%z3,%1" @@ -10195,7 +10195,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\;j\\t%2" (const_int 0)]) (match_operand:DI 2 "se_reg_or_0_operand" "dJ,0") (match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))] - "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE" + "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT" "@ mov%B4\\t%0,%z2,%1 mov%b4\\t%0,%z3,%1" @@ -10211,7 +10211,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\;j\\t%2" (const_int 0)]) (match_operand:DI 1 "se_reg_or_0_operand" "dJ,0") (match_operand:DI 2 "se_reg_or_0_operand" "0,dJ")))] - "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT" + "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_64BIT" "@ mov%T3\\t%0,%z1,%4 mov%t3\\t%0,%z2,%4" @@ -10331,7 +10331,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\;j\\t%2" (if_then_else:DI (match_dup 5) (match_operand:DI 2 "se_reg_or_0_operand" "") (match_operand:DI 3 "se_reg_or_0_operand" "")))] - "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE" + "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT" " { gen_conditional_move (operands); |