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| author | Chung-Ju Wu <jasonwucj@gmail.com> | 2018-04-25 12:32:19 +0000 |
|---|---|---|
| committer | Chung-Ju Wu <jasonwucj@gcc.gnu.org> | 2018-04-25 12:32:19 +0000 |
| commit | d3e6cab2e0c397527a4d7a06d52af04fd4a8c11a (patch) | |
| tree | a4d96b6da0b67edbf7af34654a6fcb269abe78e4 /gcc | |
| parent | ed4230b2f9bfe98205b155df607bf6c608b1b78d (diff) | |
| download | gcc-d3e6cab2e0c397527a4d7a06d52af04fd4a8c11a.zip gcc-d3e6cab2e0c397527a4d7a06d52af04fd4a8c11a.tar.gz gcc-d3e6cab2e0c397527a4d7a06d52af04fd4a8c11a.tar.bz2 | |
[NDS32] Fix bug in bit-instruction checking functions.
gcc/
* config/nds32/nds32-predicates.c (nds32_can_use_bclr_p): Mask with
GET_MODE_MASK before any checking.
(nds32_can_use_bset_p): Likewise.
(nds32_can_use_btgl_p): Likewise.
From-SVN: r259647
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/nds32/nds32-predicates.c | 9 |
2 files changed, 13 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a0adc88..6ea0aaa 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,12 @@ 2018-04-25 Chung-Ju Wu <jasonwucj@gmail.com> + * config/nds32/nds32-predicates.c (nds32_can_use_bclr_p): Mask with + GET_MODE_MASK before any checking. + (nds32_can_use_bset_p): Likewise. + (nds32_can_use_btgl_p): Likewise. + +2018-04-25 Chung-Ju Wu <jasonwucj@gmail.com> + * config/nds32/nds32-doubleword.md: New define_split pattern for illegal register number. diff --git a/gcc/config/nds32/nds32-predicates.c b/gcc/config/nds32/nds32-predicates.c index 5e01430..a670623 100644 --- a/gcc/config/nds32/nds32-predicates.c +++ b/gcc/config/nds32/nds32-predicates.c @@ -360,12 +360,13 @@ int nds32_can_use_bclr_p (int ival) { int one_bit_count; + unsigned HOST_WIDE_INT mask = GET_MODE_MASK (SImode); /* Calculate the number of 1-bit of (~ival), if there is only one 1-bit, it means the original ival has only one 0-bit, So it is ok to perform 'bclr' operation. */ - one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (~ival)); + one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (~ival) & mask); /* 'bclr' is a performance extension instruction. */ return (TARGET_EXT_PERF && (one_bit_count == 1)); @@ -376,11 +377,12 @@ int nds32_can_use_bset_p (int ival) { int one_bit_count; + unsigned HOST_WIDE_INT mask = GET_MODE_MASK (SImode); /* Caculate the number of 1-bit of ival, if there is only one 1-bit, it is ok to perform 'bset' operation. */ - one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (ival)); + one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (ival) & mask); /* 'bset' is a performance extension instruction. */ return (TARGET_EXT_PERF && (one_bit_count == 1)); @@ -391,11 +393,12 @@ int nds32_can_use_btgl_p (int ival) { int one_bit_count; + unsigned HOST_WIDE_INT mask = GET_MODE_MASK (SImode); /* Caculate the number of 1-bit of ival, if there is only one 1-bit, it is ok to perform 'btgl' operation. */ - one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (ival)); + one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (ival) & mask); /* 'btgl' is a performance extension instruction. */ return (TARGET_EXT_PERF && (one_bit_count == 1)); |