[ARM] Rewire -mfpu=fp-armv8 as VFPv5 + D32 + DP

fp-armv8 is currently defined as a double precision FPv5 with 32 D
registers *and* a special FP_ARMv8 bit. However FP for ARMv8 should only
bring 32 D registers on top of FPv5-D16 so this FP_ARMv8 bit is
spurious. As a consequence, many instruction patterns which are guarded
by TARGET_FPU_ARMV8 are unavailable to FPv5-D16 and FPv5-SP-D16.

This commit gets rid of TARGET_FPU_ARMV8 and rewire all uses to
expressions based on TARGET_VFP5, TARGET_VFPD32 and TARGET_VFP_DOUBLE.
It also redefine ISA_FP_ARMv8 to include the D32 capability to
distinguish it from FPv5-D16. At last, it sets the +fp.sp for ARMv8-R to
enable FPv5-SP-D16 (ie FP for ARMv8 with single precision only and 16 D
registers).

2017-07-14  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    * config/arm/arm-isa.h (isa_bit_FP_ARMv8): Delete enumerator.
    (ISA_FP_ARMv8): Define as ISA_FPv5 and ISA_FP_D32.
    * config/arm/arm-cpus.in (armv8-r): Define fp.sp as enabling FPv5.
    (fp-armv8): Define it as FP_ARMv8 only.
    config/arm/arm.h (TARGET_FPU_ARMV8): Delete.
    (TARGET_VFP_FP16INST): Define using TARGET_VFP5 rather than
    TARGET_FPU_ARMV8.
    config/arm/arm.c (arm_rtx_costs_internal): Replace checks against
    TARGET_FPU_ARMV8 by checks against TARGET_VFP5.
    * config/arm/arm-builtins.c (arm_builtin_vectorized_function): Define
    first ARM_CHECK_BUILTIN_MODE definition using TARGET_VFP5 rather
    than TARGET_FPU_ARMV8.
    * config/arm/arm-c.c (arm_cpu_builtins): Likewise for
    __ARM_FEATURE_NUMERIC_MAXMIN macro definition.
    * config/arm/arm.md (cmov<mode>): Condition on TARGET_VFP5 rather than
    TARGET_FPU_ARMV8.
    * config/arm/neon.md (neon_vrint): Likewise.
    (neon_vcvt): Likewise.
    (neon_<fmaxmin_op><mode>): Likewise.
    (<fmaxmin><mode>3): Likewise.
    * config/arm/vfp.md (l<vrint_pattern><su_optab><mode>si2): Likewise.
    * config/arm/predicates.md (arm_cond_move_operator): Check against
    TARGET_VFP5 rather than TARGET_FPU_ARMV8 and fix spacing.

From-SVN: r250204

11 files changed, 44 insertions, 23 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c2f3eeb..51bd2c2 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,29 @@
+2017-07-14  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* config/arm/arm-isa.h (isa_bit_FP_ARMv8): Delete enumerator.
+	(ISA_FP_ARMv8): Define as ISA_FPv5 and ISA_FP_D32.
+	* config/arm/arm-cpus.in (armv8-r): Define fp.sp as enabling FPv5.
+	(fp-armv8): Define it as FP_ARMv8 only.
+	config/arm/arm.h (TARGET_FPU_ARMV8): Delete.
+	(TARGET_VFP_FP16INST): Define using TARGET_VFP5 rather than
+	TARGET_FPU_ARMV8.
+	config/arm/arm.c (arm_rtx_costs_internal): Replace checks against
+	TARGET_FPU_ARMV8 by checks against TARGET_VFP5.
+	* config/arm/arm-builtins.c (arm_builtin_vectorized_function): Define
+	first ARM_CHECK_BUILTIN_MODE definition using TARGET_VFP5 rather
+	than TARGET_FPU_ARMV8.
+	* config/arm/arm-c.c (arm_cpu_builtins): Likewise for
+	__ARM_FEATURE_NUMERIC_MAXMIN macro definition.
+	* config/arm/arm.md (cmov<mode>): Condition on TARGET_VFP5 rather than
+	TARGET_FPU_ARMV8.
+	* config/arm/neon.md (neon_vrint): Likewise.
+	(neon_vcvt): Likewise.
+	(neon_<fmaxmin_op><mode>): Likewise.
+	(<fmaxmin><mode>3): Likewise.
+	* config/arm/vfp.md (l<vrint_pattern><su_optab><mode>si2): Likewise.
+	* config/arm/predicates.md (arm_cond_move_operator): Check against
+	TARGET_VFP5 rather than TARGET_FPU_ARMV8 and fix spacing.
+
 2017-07-14  Jackson Woodruff  <jackson.woodruff@arm.com>
 
 	* config/aarch64/aarch64.c (aarch64_print_operand): Move comments
diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index 63ee880..7504ed5 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -3098,7 +3098,7 @@ arm_builtin_vectorized_function (unsigned int fn, tree type_out, tree type_in)
    NULL_TREE is returned if no such builtin is available.  */
 #undef ARM_CHECK_BUILTIN_MODE
 #define ARM_CHECK_BUILTIN_MODE(C)    \
-  (TARGET_FPU_ARMV8   \
+  (TARGET_VFP5   \
    && flag_unsafe_math_optimizations \
    && ARM_CHECK_BUILTIN_MODE_1 (C))
 
diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c
index a3daa32..9178937 100644
--- a/gcc/config/arm/arm-c.c
+++ b/gcc/config/arm/arm-c.c
@@ -96,7 +96,7 @@ arm_cpu_builtins (struct cpp_reader* pfile)
 		       || TARGET_ARM_ARCH_ISA_THUMB >=2));
 
   def_or_undef_macro (pfile, "__ARM_FEATURE_NUMERIC_MAXMIN",
-		      TARGET_ARM_ARCH >= 8 && TARGET_NEON && TARGET_FPU_ARMV8);
+		      TARGET_ARM_ARCH >= 8 && TARGET_NEON && TARGET_VFP5);
 
   def_or_undef_macro (pfile, "__ARM_FEATURE_SIMD32", TARGET_INT_SIMD);
 
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index f35128a..e2ff297 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -389,7 +389,7 @@ begin arch armv8-r
  option crc add bit_crc32
 # fp.sp => fp-armv8 (d16); simd => simd + fp-armv8 + d32 + double precision
 # note: no fp option for fp-armv8 (d16) + double precision at the moment
- option fp.sp add FP_ARMv8
+ option fp.sp add FPv5
  option simd add FP_ARMv8 NEON
  option crypto add FP_ARMv8 CRYPTO
  option nocrypto remove ALL_CRYPTO
@@ -1390,7 +1390,7 @@ begin fpu fpv5-d16
 end fpu fpv5-d16
 
 begin fpu fp-armv8
- isa FP_ARMv8 FP_D32
+ isa FP_ARMv8
 end fpu fp-armv8
 
 begin fpu neon-fp-armv8
diff --git a/gcc/config/arm/arm-isa.h b/gcc/config/arm/arm-isa.h
index 0d66a04..dbd29ea 100644
--- a/gcc/config/arm/arm-isa.h
+++ b/gcc/config/arm/arm-isa.h
@@ -60,7 +60,6 @@ enum isa_feature
     isa_bit_VFPv4,	/* Vector floating point v4.  */
     isa_bit_FPv5,	/* Floating point v5.  */
     isa_bit_lpae,	/* ARMv7-A LPAE.  */
-    isa_bit_FP_ARMv8,	/* ARMv8 floating-point extension.  */
     isa_bit_neon,	/* Advanced SIMD instructions.  */
     isa_bit_fp16conv,	/* Conversions to/from fp16 (VFPv3 extension).  */
     isa_bit_fp_dbl,	/* Double precision operations supported.  */
@@ -143,7 +142,7 @@ enum isa_feature
    default.  isa_bit_fp16 is deliberately missing from this list.  */
 #define ISA_ALL_FPU_INTERNAL						\
   isa_bit_VFPv2, isa_bit_VFPv3, isa_bit_VFPv4, isa_bit_FPv5,		\
-  isa_bit_FP_ARMv8, isa_bit_fp16conv, isa_bit_fp_dbl, ISA_ALL_SIMD
+  isa_bit_fp16conv, isa_bit_fp_dbl, ISA_ALL_SIMD
 
 /* Similarly, but including fp16 and other extensions that aren't part of
    -mfpu support.  */
@@ -154,10 +153,10 @@ enum isa_feature
 #define ISA_VFPv3	ISA_VFPv2, isa_bit_VFPv3
 #define ISA_VFPv4	ISA_VFPv3, isa_bit_VFPv4, isa_bit_fp16conv
 #define ISA_FPv5	ISA_VFPv4, isa_bit_FPv5
-#define ISA_FP_ARMv8	ISA_FPv5, isa_bit_FP_ARMv8
 
 #define ISA_FP_DBL	isa_bit_fp_dbl
 #define ISA_FP_D32	ISA_FP_DBL, isa_bit_fp_d32
+#define ISA_FP_ARMv8	ISA_FPv5, ISA_FP_D32
 #define ISA_NEON	ISA_FP_D32, isa_bit_neon
 #define ISA_CRYPTO	ISA_NEON, isa_bit_crypto
 
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index c6101ef..f59132c 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -10755,7 +10755,7 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	{
 	  if (speed_p)
 	    *cost += extra_cost->fp[mode == DFmode].widen;
-	  if (!TARGET_FPU_ARMV8
+	  if (!TARGET_VFP5
 	      && GET_MODE (XEXP (x, 0)) == HFmode)
 	    {
 	      /* Pre v8, widening HF->DF is a two-step process, first
@@ -10849,7 +10849,7 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code,
 	      return true;
 	    }
 	  else if (GET_MODE_CLASS (mode) == MODE_FLOAT
-		   && TARGET_FPU_ARMV8)
+		   && TARGET_VFP5)
 	    {
 	      if (speed_p)
 		*cost += extra_cost->fp[mode == DFmode].roundint;
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 3156222..4f53583 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -196,10 +196,6 @@ extern tree arm_fp16_type_node;
 /* FPU supports fused-multiply-add operations.  */
 #define TARGET_FMA (bitmap_bit_p (arm_active_target.isa, isa_bit_VFPv4))
 
-/* FPU is ARMv8 compatible.  */
-#define TARGET_FPU_ARMV8					\
-  (bitmap_bit_p (arm_active_target.isa, isa_bit_FP_ARMv8))
-
 /* FPU supports Crypto extensions.  */
 #define TARGET_CRYPTO (bitmap_bit_p (arm_active_target.isa, isa_bit_crypto))
 
@@ -216,7 +212,7 @@ extern tree arm_fp16_type_node;
 
 /* FPU supports the floating point FP16 instructions for ARMv8.2 and later.  */
 #define TARGET_VFP_FP16INST \
-  (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 && arm_fp16_inst)
+  (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 && arm_fp16_inst)
 
 /* FPU supports the AdvSIMD FP16 instructions for ARMv8.2 and later.  */
 #define TARGET_NEON_FP16INST (TARGET_VFP_FP16INST && TARGET_NEON_RDMA)
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index e6e1ac5..049a78e 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -7879,7 +7879,7 @@
 			                      "<F_constraint>")
 			  (match_operand:SDF 4 "s_register_operand"
 			                      "<F_constraint>")))]
-  "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
+  "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>"
   "*
   {
     enum arm_cond_code code = maybe_get_arm_condition_code (operands[1]);
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 33b25ff..235c46d 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -751,7 +751,7 @@
         (unspec:VCVTF [(match_operand:VCVTF 1
 		         "s_register_operand" "w")]
 		NEON_VRINT))]
-  "TARGET_NEON && TARGET_FPU_ARMV8"
+  "TARGET_NEON && TARGET_VFP5"
   "vrint<nvrint_variant>.f32\\t%<V_reg>0, %<V_reg>1"
   [(set_attr "type" "neon_fp_round_<V_elem_ch><q>")]
 )
@@ -761,7 +761,7 @@
 	(FIXUORS:<V_cmp_result> (unspec:VCVTF
 			       [(match_operand:VCVTF 1 "register_operand" "w")]
 			       NEON_VCVT)))]
-  "TARGET_NEON && TARGET_FPU_ARMV8"
+  "TARGET_NEON && TARGET_VFP5"
   "vcvt<nvrint_variant>.<su>32.f32\\t%<V_reg>0, %<V_reg>1"
   [(set_attr "type" "neon_fp_to_int_<V_elem_ch><q>")
    (set_attr "predicable" "no")]
@@ -2901,7 +2901,7 @@
 	(unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w")
 		       (match_operand:VCVTF 2 "s_register_operand" "w")]
 		       VMAXMINFNM))]
-  "TARGET_NEON && TARGET_FPU_ARMV8"
+  "TARGET_NEON && TARGET_VFP5"
   "<fmaxmin_op>.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
   [(set_attr "type" "neon_fp_minmax_s<q>")]
 )
@@ -2912,7 +2912,7 @@
 	(unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w")
 		       (match_operand:VCVTF 2 "s_register_operand" "w")]
 		       VMAXMINFNM))]
-  "TARGET_NEON && TARGET_FPU_ARMV8"
+  "TARGET_NEON && TARGET_VFP5"
   "<fmaxmin_op>.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
   [(set_attr "type" "neon_fp_minmax_s<q>")]
 )
diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
index afb5d63..3e25cd1 100644
--- a/gcc/config/arm/predicates.md
+++ b/gcc/config/arm/predicates.md
@@ -350,9 +350,9 @@
 
 (define_special_predicate "arm_cond_move_operator"
   (if_then_else (match_test "arm_restrict_it")
-                (and (match_test "TARGET_FPU_ARMV8")
-                     (match_operand 0 "arm_vsel_comparison_operator"))
-                (match_operand 0 "expandable_comparison_operator")))
+		(and (match_test "TARGET_VFP5")
+		     (match_operand 0 "arm_vsel_comparison_operator"))
+		(match_operand 0 "expandable_comparison_operator")))
 
 (define_special_predicate "noov_comparison_operator"
   (match_code "lt,ge,eq,ne"))
diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index d8f77e2..23c1d67 100644
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -1997,7 +1997,7 @@
         (FIXUORS:SI (unspec:SDF
                         [(match_operand:SDF 1
                            "register_operand" "<F_constraint>")] VCVT)))]
-  "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
+  "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>"
   "vcvt<vrint_variant>.<su>32.<V_if_elem>\\t%0, %<V_reg>1"
   [(set_attr "predicable" "no")
    (set_attr "conds" "unconditional")