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| author | Uros Bizjak <ubizjak@gmail.com> | 2018-09-12 17:04:41 +0200 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2018-09-12 17:04:41 +0200 |
| commit | c749305900f8afab04948702e637579b2db2199a (patch) | |
| tree | 237297d3ff4a98158163dac0c9039ab0661a0fa4 /gcc | |
| parent | b25508e0ccf79f4c7ebd5a80e6ed3fd4a13eec51 (diff) | |
| download | gcc-c749305900f8afab04948702e637579b2db2199a.zip gcc-c749305900f8afab04948702e637579b2db2199a.tar.gz gcc-c749305900f8afab04948702e637579b2db2199a.tar.bz2 | |
i386.md (sqrt_extend<mode>xf3_i387): Remove.
* config/i386/i386.md (sqrt_extend<mode>xf3_i387): Remove.
(sqrt<mode>2): Extend operand 1 to XFmode and generate sqrtxf3 insn.
From-SVN: r264243
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/i386/i386.md | 18 |
2 files changed, 8 insertions, 15 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1da8d18..122e0d2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2018-09-12 Uros Bizjak <ubizjak@gmail.com> + + * config/i386/i386.md (sqrt_extend<mode>xf3_i387): Remove. + (sqrt<mode>2): Extend operand 1 to XFmode and generate sqrtxf3 insn. + 2018-09-12 Richard Biener <rguenther@suse.de> PR tree-optimization/87280 diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 1e7241c..2ee0f20 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -15126,19 +15126,6 @@ (set_attr "amdfam10_decode" "direct") (set_attr "bdver1_decode" "direct")]) -(define_insn "sqrt_extend<mode>xf2_i387" - [(set (match_operand:XF 0 "register_operand" "=f") - (sqrt:XF - (float_extend:XF - (match_operand:MODEF 1 "register_operand" "0"))))] - "TARGET_USE_FANCY_MATH_387" - "fsqrt" - [(set_attr "type" "fpspc") - (set_attr "mode" "XF") - (set_attr "athlon_decode" "direct") - (set_attr "amdfam10_decode" "direct") - (set_attr "bdver1_decode" "direct")]) - (define_insn "*rsqrtsf2_sse" [(set (match_operand:SF 0 "register_operand" "=x,x") (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "x,m")] @@ -15201,9 +15188,10 @@ if (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)) { rtx op0 = gen_reg_rtx (XFmode); - rtx op1 = force_reg (<MODE>mode, operands[1]); + rtx op1 = gen_reg_rtx (XFmode); - emit_insn (gen_sqrt_extend<mode>xf2_i387 (op0, op1)); + emit_insn (gen_extend<mode>xf2 (op1, operands[1])); + emit_insn (gen_sqrtxf2 (op0, op1)); emit_insn (gen_truncxf<mode>2_i387_noop_unspec (operands[0], op0)); DONE; } |