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author | Richard Sandiford <richard.sandiford@linaro.org> | 2017-11-09 15:19:15 +0000 |
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committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2017-11-09 15:19:15 +0000 |
commit | c48a8e71c8b5d3e6bdffaec85b1e3b111814cee0 (patch) | |
tree | 3c58515f2a4cb37acde83b6b85f2d30eb8f9a5b8 /gcc | |
parent | 331e1a56adf1a81c3544a8034d9e0a413ea35435 (diff) | |
download | gcc-c48a8e71c8b5d3e6bdffaec85b1e3b111814cee0.zip gcc-c48a8e71c8b5d3e6bdffaec85b1e3b111814cee0.tar.gz gcc-c48a8e71c8b5d3e6bdffaec85b1e3b111814cee0.tar.bz2 |
Add a vect_masked_store target selector
This patch adds a target selector that says whether the target
supports IFN_MASK_STORE.
2017-11-09 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* doc/sourcebuild.texi (vect_masked_store): Document.
gcc/testsuite/
* lib/target-supports.exp (check_effective_target_vect_masked_store):
New proc.
* gcc.dg/vect/vect-cselim-1.c (foo): Mention that the second loop
is vectorizable with masked stores. Update scan-tree-dump-times
accordingly.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r254597
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/ChangeLog | 6 | ||||
-rw-r--r-- | gcc/doc/sourcebuild.texi | 3 | ||||
-rw-r--r-- | gcc/testsuite/ChangeLog | 10 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/vect/vect-cselim-1.c | 5 | ||||
-rw-r--r-- | gcc/testsuite/lib/target-supports.exp | 6 |
5 files changed, 28 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 84e788f..944a3a3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -2,6 +2,12 @@ Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> + * doc/sourcebuild.texi (vect_masked_store): Document. + +2017-11-09 Richard Sandiford <richard.sandiford@linaro.org> + Alan Hayward <alan.hayward@arm.com> + David Sherwood <david.sherwood@arm.com> + * doc/sourcebuild.texi (vect_align_stack_vars): Document. 2017-11-09 Richard Sandiford <richard.sandiford@linaro.org> diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index d200f71..d5a90e5 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -1403,6 +1403,9 @@ Target supports hardware vectors of @code{long}. @item vect_long_long Target supports hardware vectors of @code{long long}. +@item vect_masked_store +Target supports vector masked stores. + @item vect_aligned_arrays Target aligns arrays to vector alignment boundary. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 8d7ad64..3ace82c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -2,6 +2,16 @@ Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> + * lib/target-supports.exp (check_effective_target_vect_masked_store): + New proc. + * gcc.dg/vect/vect-cselim-1.c (foo): Mention that the second loop + is vectorizable with masked stores. Update scan-tree-dump-times + accordingly. + +2017-11-09 Richard Sandiford <richard.sandiford@linaro.org> + Alan Hayward <alan.hayward@arm.com> + David Sherwood <david.sherwood@arm.com> + * lib/target-supports.exp (check_effective_target_vect_align_stack_vars): New proc. * gcc.dg/vect/vect-23.c: Only expect the array to be aligned if diff --git a/gcc/testsuite/gcc.dg/vect/vect-cselim-1.c b/gcc/testsuite/gcc.dg/vect/vect-cselim-1.c index 2b01013..e6ad865 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-cselim-1.c +++ b/gcc/testsuite/gcc.dg/vect/vect-cselim-1.c @@ -38,7 +38,7 @@ foo () } } - /* Not vectorizable. */ + /* Only vectorizable with masked stores. */ for (i = 0; i < N; i++) { c = in1[i].b; @@ -82,4 +82,5 @@ main (void) return 0; } -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { { vect_no_align && { ! vect_hw_misalign } } || { ! vect_strided2 } } } } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! vect_masked_store } xfail { { vect_no_align && { ! vect_hw_misalign } } || { ! vect_strided2 } } } } } */ +/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { vect_masked_store } } } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 9ef4019..54e2036 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -6433,6 +6433,12 @@ proc check_effective_target_vect_load_lanes { } { return $et_vect_load_lanes } +# Return 1 if the target supports vector masked stores. + +proc check_effective_target_vect_masked_store { } { + return 0 +} + # Return 1 if the target supports vector conditional operations, 0 otherwise. proc check_effective_target_vect_condition { } { |