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authorTerry Guo <terry.guo@arm.com>2014-11-17 07:06:54 +0000
committerXuepeng Guo <xguo@gcc.gnu.org>2014-11-17 07:06:54 +0000
commitc121b4b78ba57d9a87c3cf355319fcf8c7adc2aa (patch)
tree418601fb757b64778d7a02bae1a1ec4baeda832a /gcc
parent4696acf0d351041af6c75cf6a33703c0acdbdc76 (diff)
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thumb1.md (*addsi3_cbranch_scratch): Updated to UAL format.
gcc/ 2014-11-17 Terry Guo <terry.guo@arm.com> * config/arm/thumb1.md (*addsi3_cbranch_scratch): Updated to UAL format. gcc/testsuite/ 2014-11-17 Terry Guo <terry.guo@arm.com> * gcc.target/arm/thumb1-ual-1.c: New test. From-SVN: r217647
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/config/arm/thumb1.md4
-rw-r--r--gcc/testsuite/ChangeLog4
-rw-r--r--gcc/testsuite/gcc.target/arm/thumb1-ual-1.c87
4 files changed, 98 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index bf36bc2..543e24b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2014-11-17 Terry Guo <terry.guo@arm.com>
+
+ * config/arm/thumb1.md (*addsi3_cbranch_scratch): Updated to UAL
+ format.
+
2014-11-17 Zhenqiang Chen <zhenqiang.chen@arm.com>
* ifcvt.c (HAVE_cbranchcc4): Define.
diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md
index 3d6f80b..ddedc39 100644
--- a/gcc/config/arm/thumb1.md
+++ b/gcc/config/arm/thumb1.md
@@ -1420,13 +1420,13 @@
if (INTVAL (operands[2]) < 0)
output_asm_insn (\"subs\t%0, %1, %2\", operands);
else
- output_asm_insn (\"add\t%0, %1, %2\", operands);
+ output_asm_insn (\"adds\t%0, %1, %2\", operands);
break;
case 3:
if (INTVAL (operands[2]) < 0)
output_asm_insn (\"subs\t%0, %0, %2\", operands);
else
- output_asm_insn (\"add\t%0, %0, %2\", operands);
+ output_asm_insn (\"adds\t%0, %0, %2\", operands);
break;
}
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 4ddc713..e4b0d9c 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2014-11-17 Terry Guo <terry.guo@arm.com>
+
+ * gcc.target/arm/thumb1-ual-1.c: New test.
+
2014-11-16 Patrick Palka <ppalka@gcc.gnu.org>
PR middle-end/63790
diff --git a/gcc/testsuite/gcc.target/arm/thumb1-ual-1.c b/gcc/testsuite/gcc.target/arm/thumb1-ual-1.c
new file mode 100644
index 0000000..a2e439c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/thumb1-ual-1.c
@@ -0,0 +1,87 @@
+/* Test Thumb1 insn pattern addsi3_cbranch_scratch. */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { ! { arm_thumb1 } } } */
+
+struct real_value {
+
+ unsigned int cl : 2;
+ unsigned int decimal : 1;
+ unsigned int sign : 1;
+ unsigned int signalling : 1;
+ unsigned int canonical : 1;
+ unsigned int uexp : (32 - 6);
+ unsigned long sig[((128 + (8 * 4)) / (8 * 4))];
+};
+
+enum real_value_class {
+ rvc_zero,
+ rvc_normal,
+ rvc_inf,
+ rvc_nan
+};
+
+extern void exit(int);
+extern int foo(long long *, int, int);
+
+int
+real_to_integer (const struct real_value *r, int *fail, int precision)
+{
+ long long val[2 * (((64*(8)) + 64) / 64)];
+ int exp;
+ int words, w;
+ int result;
+
+ switch (r->cl)
+ {
+ case rvc_zero:
+ underflow:
+ return 100;
+
+ case rvc_inf:
+ case rvc_nan:
+ overflow:
+ *fail = 1;
+
+ if (r->sign)
+ return 200;
+ else
+ return 300;
+
+ case rvc_normal:
+ if (r->decimal)
+ return 400;
+
+ exp = ((int)((r)->uexp ^ (unsigned int)(1 << ((32 - 6) - 1))) - (1 << ((32 - 6) - 1)));
+ if (exp <= 0)
+ goto underflow;
+
+
+ if (exp > precision)
+ goto overflow;
+ words = (precision + 64 - 1) / 64;
+ w = words * 64;
+ for (int i = 0; i < words; i++)
+ {
+ int j = ((128 + (8 * 4)) / (8 * 4)) - (words * 2) + (i * 2);
+ if (j < 0)
+ val[i] = 0;
+ else
+ val[i] = r->sig[j];
+ j += 1;
+ if (j >= 0)
+ val[i] |= (unsigned long long) r->sig[j] << (8 * 4);
+ }
+
+
+ result = foo(val, words, w);
+
+ if (r->sign)
+ return -result;
+ else
+ return result;
+
+ default:
+ exit(2);
+ }
+}
+