diff options
| author | Segher Boessenkool <segher@kernel.crashing.org> | 2015-08-25 21:32:28 +0200 |
|---|---|---|
| committer | Segher Boessenkool <segher@gcc.gnu.org> | 2015-08-25 21:32:28 +0200 |
| commit | b733687e967cc21ae3610c3bca9250a82d66c193 (patch) | |
| tree | bc7d0e3041bce9660c62aeee3533d125ebc0bab7 /gcc | |
| parent | 693ac2ab353682796bff85e1d521eeae31a3938e (diff) | |
| download | gcc-b733687e967cc21ae3610c3bca9250a82d66c193.zip gcc-b733687e967cc21ae3610c3bca9250a82d66c193.tar.gz gcc-b733687e967cc21ae3610c3bca9250a82d66c193.tar.bz2 | |
rs6000: Fix PR67344
The "*and<mode>3_imm_dot_shifted" pattern is a define_insn_and_split,
like most "dot" patterns: if its output is not assigned cr0 but some
other cr reg, it splits to a non-dot insn and a compare.
Unfortunately that non-dot insn will clobber cr0 as well. We could
add another clobber (with "=X,x"), but then that second alternative
is never useful; instead, just remove that second alternative.
2015-08-25 Segher Boessenkool <segher@kernel.crashing.org>
PR target/67344
* config/rs6000/rs6000.md (*and<mode>3_imm_dot_shifted): Change to
a define_insn, remove second alternative.
From-SVN: r227182
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 29 |
2 files changed, 14 insertions, 21 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fae266d..6d0e1e1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2015-08-25 Segher Boessenkool <segher@kernel.crashing.org> + + PR target/67344 + * config/rs6000/rs6000.md (*and<mode>3_imm_dot_shifted): Change to + a define_insn, remove second alternative. + 2015-08-25 Thomas Schwinge <thomas@codesourcery.com> Joseph Myers <joseph@codesourcery.com> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index e7d97df..6063242 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -3037,15 +3037,15 @@ (set_attr "dot" "yes") (set_attr "length" "4,8")]) -(define_insn_and_split "*and<mode>3_imm_dot_shifted" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") +(define_insn "*and<mode>3_imm_dot_shifted" + [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC (and:GPR - (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r") - (match_operand:SI 4 "const_int_operand" "n,n")) - (match_operand:GPR 2 "const_int_operand" "n,n")) + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r") + (match_operand:SI 4 "const_int_operand" "n")) + (match_operand:GPR 2 "const_int_operand" "n")) (const_int 0))) - (clobber (match_scratch:GPR 0 "=r,r"))] + (clobber (match_scratch:GPR 0 "=r"))] "logical_const_operand (GEN_INT (UINTVAL (operands[2]) << INTVAL (operands[4])), DImode) @@ -3054,23 +3054,10 @@ && rs6000_gen_cell_microcode" { operands[2] = GEN_INT (UINTVAL (operands[2]) << INTVAL (operands[4])); - if (which_alternative == 0) - return "andi%e2. %0,%1,%u2"; - else - return "#"; + return "andi%e2. %0,%1,%u2"; } - "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)" - [(set (match_dup 0) - (and:GPR (lshiftrt:GPR (match_dup 1) - (match_dup 4)) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "" [(set_attr "type" "logical") - (set_attr "dot" "yes") - (set_attr "length" "4,8")]) + (set_attr "dot" "yes")]) (define_insn "and<mode>3_mask" |