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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2016-11-16 09:02:18 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <ktkachov@gcc.gnu.org> | 2016-11-16 09:02:18 +0000 |
| commit | b6adf1c5fb249497a0f35a2ffb9897b35764d3c9 (patch) | |
| tree | 7a336dc9bce0a19d51fc9a23758628f25d735efc /gcc | |
| parent | 510d73a0350e946becdf316b130a7197809124f6 (diff) | |
| download | gcc-b6adf1c5fb249497a0f35a2ffb9897b35764d3c9.zip gcc-b6adf1c5fb249497a0f35a2ffb9897b35764d3c9.tar.gz gcc-b6adf1c5fb249497a0f35a2ffb9897b35764d3c9.tar.bz2 | |
[ARM] PR target/78364: Add proper restrictions to zero and sign_extract patterns operands
PR target/78364
* config/arm/arm.md (*extv_reg): Restrict operands 2 and 3 to the
proper ranges for an SBFX instruction.
(extzv_t2): Likewise for UBFX.
From-SVN: r242471
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 16 |
2 files changed, 17 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3f6f3ce..ed37d6d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2016-11-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + PR target/78364 + * config/arm/arm.md (*extv_reg): Restrict operands 2 and 3 to the + proper ranges for an SBFX instruction. + (extzv_t2): Likewise for UBFX. + 2016-11-16 Richard Biener <rguenther@suse.de> PR tree-optimization/78348 diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 8393f65..761c52f 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -4546,9 +4546,11 @@ (define_insn "*extv_reg" [(set (match_operand:SI 0 "s_register_operand" "=r") (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "const_int_M_operand" "M") - (match_operand:SI 3 "const_int_M_operand" "M")))] - "arm_arch_thumb2" + (match_operand:SI 2 "const_int_operand" "n") + (match_operand:SI 3 "const_int_operand" "n")))] + "arm_arch_thumb2 + && IN_RANGE (INTVAL (operands[3]), 0, 31) + && IN_RANGE (INTVAL (operands[2]), 1, 32 - INTVAL (operands[3]))" "sbfx%?\t%0, %1, %3, %2" [(set_attr "length" "4") (set_attr "predicable" "yes") @@ -4559,9 +4561,11 @@ (define_insn "extzv_t2" [(set (match_operand:SI 0 "s_register_operand" "=r") (zero_extract:SI (match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "const_int_M_operand" "M") - (match_operand:SI 3 "const_int_M_operand" "M")))] - "arm_arch_thumb2" + (match_operand:SI 2 "const_int_operand" "n") + (match_operand:SI 3 "const_int_operand" "n")))] + "arm_arch_thumb2 + && IN_RANGE (INTVAL (operands[3]), 0, 31) + && IN_RANGE (INTVAL (operands[2]), 1, 32 - INTVAL (operands[3]))" "ubfx%?\t%0, %1, %3, %2" [(set_attr "length" "4") (set_attr "predicable" "yes") |