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| author | Tejas Belagod <tejas.belagod@arm.com> | 2013-01-08 16:23:38 +0000 |
|---|---|---|
| committer | Tejas Belagod <belagod@gcc.gnu.org> | 2013-01-08 16:23:38 +0000 |
| commit | b4208463a3f454e3b10e3a3a306ee7416897c301 (patch) | |
| tree | 10be05fb65446a435e87d960e17fddfe8668ff76 /gcc | |
| parent | a02ad1aa17974f1c98a4f904e6f09d6a50f00dc0 (diff) | |
| download | gcc-b4208463a3f454e3b10e3a3a306ee7416897c301.zip gcc-b4208463a3f454e3b10e3a3a306ee7416897c301.tar.gz gcc-b4208463a3f454e3b10e3a3a306ee7416897c301.tar.bz2 | |
vect-mull-compile.c: Explicitly scan for instructions generated instead of number of occurances.
2013-01-08 Tejas Belagod <tejas.belagod@arm.com>
* gcc.target/aarch64/vect-mull-compile.c: Explicitly scan for
instructions generated instead of number of occurances.
From-SVN: r195024
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/vect-mull-compile.c | 16 |
2 files changed, 17 insertions, 4 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 303a4bc..eab4c35 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2013-01-08 Tejas Belagod <tejas.belagod@arm.com> + + * gcc.target/aarch64/vect-mull-compile.c: Explicitly scan for + instructions generated instead of number of occurances. + 2013-01-08 James Greenhalgh <james.greenhalgh@arm.com> * gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c: New. diff --git a/gcc/testsuite/gcc.target/aarch64/vect-mull-compile.c b/gcc/testsuite/gcc.target/aarch64/vect-mull-compile.c index e51eaee..e90c97f 100644 --- a/gcc/testsuite/gcc.target/aarch64/vect-mull-compile.c +++ b/gcc/testsuite/gcc.target/aarch64/vect-mull-compile.c @@ -10,7 +10,15 @@ DEF_MULL2 (DEF_MULLB) DEF_MULL2 (DEF_MULLH) DEF_MULL2 (DEF_MULLS) -/* { dg-final { scan-assembler-times "smull v" 3 } } */ -/* { dg-final { scan-assembler-times "smull2 v" 3 } } */ -/* { dg-final { scan-assembler-times "umull v" 3 } } */ -/* { dg-final { scan-assembler-times "umull2 v" 3 } } */ +/* { dg-final { scan-assembler "smull\\tv\[0-9\]+\.8h"} } */ +/* { dg-final { scan-assembler "smull\\tv\[0-9\]+\.4s"} } */ +/* { dg-final { scan-assembler "smull\\tv\[0-9\]+\.2d"} } */ +/* { dg-final { scan-assembler "umull\\tv\[0-9\]+\.8h"} } */ +/* { dg-final { scan-assembler "umull\\tv\[0-9\]+\.4s"} } */ +/* { dg-final { scan-assembler "umull\\tv\[0-9\]+\.2d"} } */ +/* { dg-final { scan-assembler "smull2\\tv\[0-9\]+\.8h"} } */ +/* { dg-final { scan-assembler "smull2\\tv\[0-9\]+\.4s"} } */ +/* { dg-final { scan-assembler "smull2\\tv\[0-9\]+\.2d"} } */ +/* { dg-final { scan-assembler "umull2\\tv\[0-9\]+\.8h"} } */ +/* { dg-final { scan-assembler "umull2\\tv\[0-9\]+\.4s"} } */ +/* { dg-final { scan-assembler "umull2\\tv\[0-9\]+\.2d"} } */ |