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| author | Uros Bizjak <ubizjak@gmail.com> | 2011-11-01 23:46:07 +0100 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2011-11-01 23:46:07 +0100 |
| commit | a8b5c4e82758a97a945d0e768112be8c85dbf86f (patch) | |
| tree | 7506334effdd794cb22dd6d3158d73e865342ce2 /gcc | |
| parent | f4496f0fecea4060d1a6e036d80b092aa564f7f3 (diff) | |
| download | gcc-a8b5c4e82758a97a945d0e768112be8c85dbf86f.zip gcc-a8b5c4e82758a97a945d0e768112be8c85dbf86f.tar.gz gcc-a8b5c4e82758a97a945d0e768112be8c85dbf86f.tar.bz2 | |
i386.md (splitters for int-float conversion): Use SUBREG_REG on SUBREGs in splitter constraints.
* config/i386/i386.md (splitters for int-float conversion): Use
SUBREG_REG on SUBREGs in splitter constraints.
From-SVN: r180748
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 2 | ||||
| -rw-r--r-- | gcc/config/i386/i386.md | 36 |
2 files changed, 28 insertions, 10 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0a22086..771a4a2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -5,7 +5,7 @@ 2011-11-01 Uros Bizjak <ubizjak@gmail.com> * config/i386/i386.md (splitters for int-float conversion): Use - reg_or_subregno in splitter constraints. + SUBREG_REG on SUBREGs in splitter constraints. 2011-11-01 Jakub Jelinek <jakub@redhat.com> diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 4fae10d..11c866b 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -4920,7 +4920,9 @@ && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387 && TARGET_INTER_UNIT_CONVERSIONS && reload_completed - && SSE_REGNO_P (reg_or_subregno (operands[0]))" + && (SSE_REG_P (operands[0]) + || (GET_CODE (operands[0]) == SUBREG + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(set (match_dup 0) (float:MODEF (match_dup 1)))]) (define_split @@ -4931,7 +4933,9 @@ && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387 && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun)) && reload_completed - && SSE_REGNO_P (reg_or_subregno (operands[0]))" + && (SSE_REG_P (operands[0]) + || (GET_CODE (operands[0]) == SUBREG + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (float:MODEF (match_dup 2)))]) @@ -5020,7 +5024,9 @@ "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) && reload_completed - && SSE_REGNO_P (reg_or_subregno (operands[0]))" + && (SSE_REG_P (operands[0]) + || (GET_CODE (operands[0]) == SUBREG + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(const_int 0)] { rtx op1 = operands[1]; @@ -5061,7 +5067,9 @@ "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) && reload_completed - && SSE_REGNO_P (reg_or_subregno (operands[0]))" + && (SSE_REG_P (operands[0]) + || (GET_CODE (operands[0]) == SUBREG + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(const_int 0)] { operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0], @@ -5083,7 +5091,9 @@ "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) && reload_completed - && SSE_REGNO_P (reg_or_subregno (operands[0]))" + && (SSE_REG_P (operands[0]) + || (GET_CODE (operands[0]) == SUBREG + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(const_int 0)] { rtx op1 = operands[1]; @@ -5127,7 +5137,9 @@ "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) && reload_completed - && SSE_REGNO_P (reg_or_subregno (operands[0]))" + && (SSE_REG_P (operands[0]) + || (GET_CODE (operands[0]) == SUBREG + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(const_int 0)] { operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0], @@ -5188,7 +5200,9 @@ && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH && (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun)) && reload_completed - && SSE_REGNO_P (reg_or_subregno (operands[0]))" + && (SSE_REG_P (operands[0]) + || (GET_CODE (operands[0]) == SUBREG + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(set (match_dup 0) (float:MODEF (match_dup 1)))]) (define_insn "*float<SWI48x:mode><MODEF:mode>2_sse_nointerunit" @@ -5221,7 +5235,9 @@ && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun)) && reload_completed - && SSE_REGNO_P (reg_or_subregno (operands[0]))" + && (SSE_REG_P (operands[0]) + || (GET_CODE (operands[0]) == SUBREG + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (float:MODEF (match_dup 2)))]) @@ -5232,7 +5248,9 @@ "(<SWI48x:MODE>mode != DImode || TARGET_64BIT) && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH && reload_completed - && SSE_REGNO_P (reg_or_subregno (operands[0]))" + && (SSE_REG_P (operands[0]) + || (GET_CODE (operands[0]) == SUBREG + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(set (match_dup 0) (float:MODEF (match_dup 1)))]) (define_insn "*float<SWI48x:mode><X87MODEF:mode>2_i387_with_temp" |