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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2013-11-26 15:06:06 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <ktkachov@gcc.gnu.org> | 2013-11-26 15:06:06 +0000 |
| commit | a866fa46ea86c6843bd14be5393e945b76a80334 (patch) | |
| tree | ad06086ca6ec3512780015acb1ad659a1a1c761e /gcc | |
| parent | 40f213e6f5bf36a5678a1ff5a75773d02df67f53 (diff) | |
| download | gcc-a866fa46ea86c6843bd14be5393e945b76a80334.zip gcc-a866fa46ea86c6843bd14be5393e945b76a80334.tar.gz gcc-a866fa46ea86c6843bd14be5393e945b76a80334.tar.bz2 | |
re PR target/59290 ([ARM] regression on negdi-2.c (big-endian))
[gcc/]
2013-11-26 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/59290
* config/arm/arm.md (*zextendsidi_negsi): New pattern.
* config/arm/arm.c (arm_new_rtx_costs): Initialise cost correctly
for zero_extend case.
[gcc/testsuite/]
2013-11-26 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/59290
* gcc.target/arm/negdi-2.c: Scan more general register names.
From-SVN: r205394
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 2 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 18 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/negdi-2.c | 4 |
5 files changed, 34 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d63759e..61cbbc4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2013-11-26 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + PR target/59290 + * config/arm/arm.md (*zextendsidi_negsi): New pattern. + * config/arm/arm.c (arm_new_rtx_costs): Initialise cost correctly + for zero_extend case. + 2013-11-26 H.J. Lu <hongjiu.lu@intel.com> PR bootstrap/55552 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 4af6c05..f88ebbc 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -10130,6 +10130,8 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, if (speed_p) *cost += 2 * extra_cost->alu.shift; } + else /* GET_MODE (XEXP (x, 0)) == SImode. */ + *cost = COSTS_N_INSNS (1); /* Widening beyond 32-bits requires one more insn. */ if (mode == DImode) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 16095fa..dd73366 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -4718,6 +4718,24 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "") +(define_insn_and_split "*zextendsidi_negsi" + [(set (match_operand:DI 0 "s_register_operand" "=r") + (zero_extend:DI (neg:SI (match_operand:SI 1 "s_register_operand" "r"))))] + "TARGET_32BIT" + "#" + "" + [(set (match_dup 2) + (neg:SI (match_dup 1))) + (set (match_dup 3) + (const_int 0))] + { + operands[2] = gen_lowpart (SImode, operands[0]); + operands[3] = gen_highpart (SImode, operands[0]); + } + [(set_attr "length" "8") + (set_attr "type" "multiple")] +) + ;; Negate an extended 32-bit value. (define_insn_and_split "*negdi_extendsidi" [(set (match_operand:DI 0 "s_register_operand" "=l,r") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2ae5300..84abf1d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2013-11-26 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + PR target/59290 + * gcc.target/arm/negdi-2.c: Scan more general register names. + 2013-11-26 Terry Guo <terry.guo@arm.com> * gcc.target/arm/thumb1-pic-high-reg.c: New case. diff --git a/gcc/testsuite/gcc.target/arm/negdi-2.c b/gcc/testsuite/gcc.target/arm/negdi-2.c index 96bbcab..4444c20 100644 --- a/gcc/testsuite/gcc.target/arm/negdi-2.c +++ b/gcc/testsuite/gcc.target/arm/negdi-2.c @@ -11,6 +11,6 @@ Expected output: rsb r0, r0, #0 mov r1, #0 */ -/* { dg-final { scan-assembler-times "rsb\\tr0, r0, #0" 1 { target { arm_nothumb } } } } */ -/* { dg-final { scan-assembler-times "negs\\tr0, r0" 1 { target { ! arm_nothumb } } } } */ +/* { dg-final { scan-assembler-times "rsb\\t...?, ...?, #0" 1 { target { arm_nothumb } } } } */ +/* { dg-final { scan-assembler-times "negs\\t...?, ...?" 1 { target { ! arm_nothumb } } } } */ /* { dg-final { scan-assembler-times "mov" 1 } } */ |