aboutsummaryrefslogtreecommitdiff
path: root/gcc
diff options
context:
space:
mode:
authorXinyu Qi <xyqi@marvell.com>2013-03-26 14:01:24 +0000
committerRamana Radhakrishnan <ramana@gcc.gnu.org>2013-03-26 14:01:24 +0000
commita76213b9b371f5dd641bb7b44201d3a57945544d (patch)
tree53320f6441b496cecc01c4c7071b75db89a417f7 /gcc
parent37ff93553cf2deab79a4f08aca129559b9ff52dc (diff)
downloadgcc-a76213b9b371f5dd641bb7b44201d3a57945544d.zip
gcc-a76213b9b371f5dd641bb7b44201d3a57945544d.tar.gz
gcc-a76213b9b371f5dd641bb7b44201d3a57945544d.tar.bz2
For Xinyu Qi - Fix define_constants for WCGR.
From-SVN: r197104
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog6
-rw-r--r--gcc/config/arm/arm.h2
-rw-r--r--gcc/config/arm/iwmmxt.md10
3 files changed, 13 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d5f829f..34721f7 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2013-03-26 Xinyu Qi <xyqi@marvell.com>
+
+ * config/arm/arm.h (FIRST_IWMMXT_GR_REGNUM): Add comment.
+ * config/arm/iwmmxt.md (WCGR0): Update.
+ (WCGR1, WCGR2, WCGR3): Likewise.
+
2013-03-26 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (*movdfcc_1): Merge with *movdfcc_1_rex64.
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 39eb2a1..beee458 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -955,6 +955,8 @@ extern int prefer_neon_for_64bits;
#define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1)
#define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15)
+
+/* Need to sync with WCGR in iwmmxt.md. */
#define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1)
#define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3)
diff --git a/gcc/config/arm/iwmmxt.md b/gcc/config/arm/iwmmxt.md
index 9e79454..ac4867b 100644
--- a/gcc/config/arm/iwmmxt.md
+++ b/gcc/config/arm/iwmmxt.md
@@ -18,12 +18,12 @@
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
-;; Register numbers
+;; Register numbers. Need to sync with FIRST_IWMMXT_GR_REGNUM in arm.h
(define_constants
- [(WCGR0 43)
- (WCGR1 44)
- (WCGR2 45)
- (WCGR3 46)
+ [(WCGR0 96)
+ (WCGR1 97)
+ (WCGR2 98)
+ (WCGR3 99)
]
)