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| author | Segher Boessenkool <segher@kernel.crashing.org> | 2018-10-05 21:40:36 +0200 |
|---|---|---|
| committer | Segher Boessenkool <segher@gcc.gnu.org> | 2018-10-05 21:40:36 +0200 |
| commit | a3a81f292256069546bc2b0b9ebddb229af117b1 (patch) | |
| tree | 537fb73a13ed33e3cb5d7684449a7ff635db1ae8 /gcc | |
| parent | c1ec62f1fb21fd7dd4f83fb6724d9b210b2e59f2 (diff) | |
| download | gcc-a3a81f292256069546bc2b0b9ebddb229af117b1.zip gcc-a3a81f292256069546bc2b0b9ebddb229af117b1.tar.gz gcc-a3a81f292256069546bc2b0b9ebddb229af117b1.tar.bz2 | |
rs6000: Some mfcr pattern simplification
* config/rs6000/rs6000.md (unnamed mfcr scc_comparison_operator
patterns): Merge SI and DI patterns to a GPR pattern.
(unnamed define_insn and define_split for record form of that): Merge
to a single define_insn_and_split pattern.
From-SVN: r264889
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 43 |
2 files changed, 17 insertions, 33 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 53c9c89..8d754af 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2018-10-05 Segher Boessenkool <segher@kernel.crashing.org> + + * config/rs6000/rs6000.md (unnamed mfcr scc_comparison_operator + patterns): Merge SI and DI patterns to a GPR pattern. + (unnamed define_insn and define_split for record form of that): Merge + to a single define_insn_and_split pattern. + 2018-10-05 David Malcolm <dmalcolm@redhat.com> PR c++/56856 diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 5db3e57..0e7cf35 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -11765,10 +11765,10 @@ ;; cases the insns below which don't use an intermediate CR field will ;; be used instead. (define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (match_operator:SI 1 "scc_comparison_operator" - [(match_operand 2 "cc_reg_operand" "y") - (const_int 0)]))] + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (match_operator:GPR 1 "scc_comparison_operator" + [(match_operand 2 "cc_reg_operand" "y") + (const_int 0)]))] "" "mfcr %0%Q2\;rlwinm %0,%0,%J1,1" [(set (attr "type") @@ -11778,21 +11778,7 @@ (const_string "mfcr"))) (set_attr "length" "8")]) -(define_insn "" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r") - (match_operator:DI 1 "scc_comparison_operator" - [(match_operand 2 "cc_reg_operand" "y") - (const_int 0)]))] - "TARGET_POWERPC64" - "mfcr %0%Q2\;rlwinm %0,%0,%J1,1" - [(set (attr "type") - (cond [(match_test "TARGET_MFCRF") - (const_string "mfcrf") - ] - (const_string "mfcr"))) - (set_attr "length" "8")]) - -(define_insn "" +(define_insn_and_split "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (match_operator:SI 1 "scc_comparison_operator" [(match_operand 2 "cc_reg_operand" "y,y") @@ -11804,25 +11790,16 @@ "@ mfcr %3%Q2\;rlwinm. %3,%3,%J1,1 #" - [(set_attr "type" "shift") - (set_attr "dot" "yes") - (set_attr "length" "8,16")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand") - (compare:CC (match_operator:SI 1 "scc_comparison_operator" - [(match_operand 2 "cc_reg_operand") - (const_int 0)]) - (const_int 0))) - (set (match_operand:SI 3 "gpc_reg_operand") - (match_op_dup 1 [(match_dup 2) (const_int 0)]))] - "TARGET_32BIT && reload_completed" + "&& reload_completed" [(set (match_dup 3) (match_op_dup 1 [(match_dup 2) (const_int 0)])) (set (match_dup 0) (compare:CC (match_dup 3) (const_int 0)))] - "") + "" + [(set_attr "type" "shift") + (set_attr "dot" "yes") + (set_attr "length" "8,16")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |