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| author | Matthew Gretton-Dann <matthew.gretton-dann@arm.com> | 2012-03-13 10:53:57 +0000 |
|---|---|---|
| committer | Matthew Gretton-Dann <mgretton@gcc.gnu.org> | 2012-03-13 10:53:57 +0000 |
| commit | a0a6e3f70ada6957540ae9c57c255338cebe54d3 (patch) | |
| tree | 42462955e0d31178ecd401ffc15b2dedfc518665 /gcc | |
| parent | 9ec960239680726720385bcb82725d0c14204546 (diff) | |
| download | gcc-a0a6e3f70ada6957540ae9c57c255338cebe54d3.zip gcc-a0a6e3f70ada6957540ae9c57c255338cebe54d3.tar.gz gcc-a0a6e3f70ada6957540ae9c57c255338cebe54d3.tar.bz2 | |
neon.ml (ops): Fixup expected instructions for unsigned vector compares.
* gcc/config/arm/neon.ml (ops): Fixup expected instructions for
unsigned vector compares.
From-SVN: r185328
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/arm/neon.ml | 22 |
2 files changed, 21 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index dd02f18..c8de4f9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2012-03-13 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> + + * config/arm/neon.ml (ops): Fixup expected instructions for + unsigned vector compares. + 2012-03-13 Uros Bizjak <ubizjak@gmail.com> * config/i386/i386.c (ix86_decompose_address): Prevent %fs:(%reg) diff --git a/gcc/config/arm/neon.ml b/gcc/config/arm/neon.ml index 363e55c..85eb5ec 100644 --- a/gcc/config/arm/neon.ml +++ b/gcc/config/arm/neon.ml @@ -780,14 +780,19 @@ let ops = (* Comparison, greater-than or equal. *) Vcge, [], All (3, Dreg), "vcge", cmp_sign_matters, F32 :: s_8_32; - Vcge, [Builtin_name "vcgeu"], All (3, Dreg), "vcge", cmp_sign_matters, u_8_32; + Vcge, [Instruction_name ["vcge"]; Builtin_name "vcgeu"], + All (3, Dreg), "vcge", cmp_sign_matters, + u_8_32; Vcge, [], All (3, Qreg), "vcgeQ", cmp_sign_matters, F32 :: s_8_32; - Vcge, [Builtin_name "vcgeu"], All (3, Qreg), "vcgeQ", cmp_sign_matters, u_8_32; + Vcge, [Instruction_name ["vcge"]; Builtin_name "vcgeu"], + All (3, Qreg), "vcgeQ", cmp_sign_matters, + u_8_32; (* Comparison, less-than or equal. *) Vcle, [Flipped "vcge"], All (3, Dreg), "vcle", cmp_sign_matters, F32 :: s_8_32; - Vcle, [Flipped "vcgeu"], All (3, Dreg), "vcle", cmp_sign_matters, + Vcle, [Instruction_name ["vcge"]; Flipped "vcgeu"], + All (3, Dreg), "vcle", cmp_sign_matters, u_8_32; Vcle, [Instruction_name ["vcge"]; Flipped "vcgeQ"], All (3, Qreg), "vcleQ", cmp_sign_matters, @@ -798,14 +803,19 @@ let ops = (* Comparison, greater-than. *) Vcgt, [], All (3, Dreg), "vcgt", cmp_sign_matters, F32 :: s_8_32; - Vcgt, [Builtin_name "vcgtu"], All (3, Dreg), "vcgt", cmp_sign_matters, u_8_32; + Vcgt, [Instruction_name ["vcgt"]; Builtin_name "vcgtu"], + All (3, Dreg), "vcgt", cmp_sign_matters, + u_8_32; Vcgt, [], All (3, Qreg), "vcgtQ", cmp_sign_matters, F32 :: s_8_32; - Vcgt, [Builtin_name "vcgtu"], All (3, Qreg), "vcgtQ", cmp_sign_matters, u_8_32; + Vcgt, [Instruction_name ["vcgt"]; Builtin_name "vcgtu"], + All (3, Qreg), "vcgtQ", cmp_sign_matters, + u_8_32; (* Comparison, less-than. *) Vclt, [Flipped "vcgt"], All (3, Dreg), "vclt", cmp_sign_matters, F32 :: s_8_32; - Vclt, [Flipped "vcgtu"], All (3, Dreg), "vclt", cmp_sign_matters, + Vclt, [Instruction_name ["vcgt"]; Flipped "vcgtu"], + All (3, Dreg), "vclt", cmp_sign_matters, u_8_32; Vclt, [Instruction_name ["vcgt"]; Flipped "vcgtQ"], All (3, Qreg), "vcltQ", cmp_sign_matters, |