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| author | Tejas Belagod <tejas.belagod@arm.com> | 2013-01-08 16:21:51 +0000 |
|---|---|---|
| committer | Tejas Belagod <belagod@gcc.gnu.org> | 2013-01-08 16:21:51 +0000 |
| commit | a02ad1aa17974f1c98a4f904e6f09d6a50f00dc0 (patch) | |
| tree | 4ae2fdcce21bd2544802ea6e7203d8c0c69e1180 /gcc | |
| parent | 83ffd96445eddb41a8f296e463e40d56e851f3b9 (diff) | |
| download | gcc-a02ad1aa17974f1c98a4f904e6f09d6a50f00dc0.zip gcc-a02ad1aa17974f1c98a4f904e6f09d6a50f00dc0.tar.gz gcc-a02ad1aa17974f1c98a4f904e6f09d6a50f00dc0.tar.bz2 | |
aarch64-simd.md (aarch64_simd_vec_<su>mult_lo_<mode>, [...]): Separate instruction and operand with tab instead of space.
2013-01-08 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_simd_vec_<su>mult_lo_<mode>,
aarch64_simd_vec_<su>mult_hi_<mode>): Separate instruction and operand
with tab instead of space.
From-SVN: r195023
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 4 |
2 files changed, 8 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 78eb7c0..0862196 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2013-01-08 Tejas Belagod <tejas.belagod@arm.com> + + * config/aarch64/aarch64-simd.md (aarch64_simd_vec_<su>mult_lo_<mode>, + aarch64_simd_vec_<su>mult_hi_<mode>): Separate instruction and operand + with tab instead of space. + 2013-01-08 Nick Clifton <nickc@redhat.com> * config/rl78/rl78.c (rl78_expand_prologue): Always select diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index e6655e8..cbf8b88 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1054,7 +1054,7 @@ (match_operand:VQW 2 "register_operand" "w") (match_dup 3)))))] "TARGET_SIMD" - "<su>mull %0.<Vwtype>, %1.<Vhalftype>, %2.<Vhalftype>" + "<su>mull\\t%0.<Vwtype>, %1.<Vhalftype>, %2.<Vhalftype>" [(set_attr "simd_type" "simd_mull") (set_attr "simd_mode" "<MODE>")] ) @@ -1082,7 +1082,7 @@ (match_operand:VQW 2 "register_operand" "w") (match_dup 3)))))] "TARGET_SIMD" - "<su>mull2 %0.<Vwtype>, %1.<Vtype>, %2.<Vtype>" + "<su>mull2\\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>" [(set_attr "simd_type" "simd_mull") (set_attr "simd_mode" "<MODE>")] ) |