aboutsummaryrefslogtreecommitdiff
path: root/gcc
diff options
context:
space:
mode:
authorJakub Jelinek <jakub@redhat.com>2016-05-06 15:16:00 +0200
committerJakub Jelinek <jakub@gcc.gnu.org>2016-05-06 15:16:00 +0200
commit9bdf001b7a2232753e4a92582218bb4f24c8d809 (patch)
tree46c43c24add8e3c166ee21f22b9db4c0b7fc59bc /gcc
parentdd3b6464c54804dcfa82bba61a10c46706a65bed (diff)
downloadgcc-9bdf001b7a2232753e4a92582218bb4f24c8d809.zip
gcc-9bdf001b7a2232753e4a92582218bb4f24c8d809.tar.gz
gcc-9bdf001b7a2232753e4a92582218bb4f24c8d809.tar.bz2
sse.md (*<code>v8hi3, [...]): Add avx512bw alternative.
* config/i386/sse.md (*<code>v8hi3, *<code>v16qi3): Add avx512bw alternative. From-SVN: r235973
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog3
-rw-r--r--gcc/config/i386/sse.md30
2 files changed, 19 insertions, 14 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 886905d..1fbc350 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,8 @@
2016-05-06 Jakub Jelinek <jakub@redhat.com>
+ * config/i386/sse.md (*<code>v8hi3, *<code>v16qi3): Add
+ avx512bw alternative.
+
* config/i386/sse.md (<mask_codefor>ashr<mode>3<mask_name>): Move
before the ashr<mode>3 pattern.
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index bb0d217..26463e5 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -10458,19 +10458,20 @@
(set_attr "mode" "TI")])
(define_insn "*<code>v8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x,x")
+ [(set (match_operand:V8HI 0 "register_operand" "=x,x,v")
(smaxmin:V8HI
- (match_operand:V8HI 1 "vector_operand" "%0,x")
- (match_operand:V8HI 2 "vector_operand" "xBm,xm")))]
+ (match_operand:V8HI 1 "vector_operand" "%0,x,v")
+ (match_operand:V8HI 2 "vector_operand" "xBm,xm,vm")))]
"TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V8HImode, operands)"
"@
p<maxmin_int>w\t{%2, %0|%0, %2}
+ vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}
vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "isa" "noavx,avx")
+ [(set_attr "isa" "noavx,avx,avx512bw")
(set_attr "type" "sseiadd")
- (set_attr "prefix_data16" "1,*")
- (set_attr "prefix_extra" "*,1")
- (set_attr "prefix" "orig,vex")
+ (set_attr "prefix_data16" "1,*,*")
+ (set_attr "prefix_extra" "*,1,1")
+ (set_attr "prefix" "orig,vex,evex")
(set_attr "mode" "TI")])
(define_expand "<code><mode>3"
@@ -10542,19 +10543,20 @@
(set_attr "mode" "TI")])
(define_insn "*<code>v16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "=x,x")
+ [(set (match_operand:V16QI 0 "register_operand" "=x,x,v")
(umaxmin:V16QI
- (match_operand:V16QI 1 "vector_operand" "%0,x")
- (match_operand:V16QI 2 "vector_operand" "xBm,xm")))]
+ (match_operand:V16QI 1 "vector_operand" "%0,x,v")
+ (match_operand:V16QI 2 "vector_operand" "xBm,xm,vm")))]
"TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V16QImode, operands)"
"@
p<maxmin_int>b\t{%2, %0|%0, %2}
+ vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}
vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "isa" "noavx,avx")
+ [(set_attr "isa" "noavx,avx,avx512bw")
(set_attr "type" "sseiadd")
- (set_attr "prefix_data16" "1,*")
- (set_attr "prefix_extra" "*,1")
- (set_attr "prefix" "orig,vex")
+ (set_attr "prefix_data16" "1,*,*")
+ (set_attr "prefix_extra" "*,1,1")
+ (set_attr "prefix" "orig,vex,evex")
(set_attr "mode" "TI")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;