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| author | Claudiu Zissulescu <claziss@synopsys.com> | 2018-04-23 11:55:14 +0200 |
|---|---|---|
| committer | Claudiu Zissulescu <claziss@gcc.gnu.org> | 2018-04-23 11:55:14 +0200 |
| commit | 9ba5e5fceeff0d9a752b8c0a00344b3a187d08bb (patch) | |
| tree | 0a0acdfb013a4594fd3eac4b4293a250dfe477eb /gcc | |
| parent | 31d2e01ad472f11ebfd9cc3405238e90cf25a09c (diff) | |
| download | gcc-9ba5e5fceeff0d9a752b8c0a00344b3a187d08bb.zip gcc-9ba5e5fceeff0d9a752b8c0a00344b3a187d08bb.tar.gz gcc-9ba5e5fceeff0d9a752b8c0a00344b3a187d08bb.tar.bz2 | |
[ARC] Fix FLS, SETI patterns.
Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.md ("vunspec"): Delete it, unify all the unspec
enums into a single definition.
(fls): Fix predicates and printing.
(seti): Likewise.
From-SVN: r259558
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/arc/arc.md | 14 |
2 files changed, 12 insertions, 9 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6044fbc..4dcf45e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,12 @@ 2018-04-23 Claudiu Zissulescu <claziss@synopsys.com> + * config/arc/arc.md ("vunspec"): Delete it, unify all the unspec + enums into a single definition. + (fls): Fix predicates and printing. + (seti): Likewise. + +2018-04-23 Claudiu Zissulescu <claziss@synopsys.com> + * config/arc/arc-protos.h (check_if_valid_sleep_operand): Remove. * config/arc/arc.c (arc_expand_builtin): Sleep accepts registers and short u6 immediate. diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index c4bc300..d19e99d 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -136,9 +136,7 @@ UNSPEC_ARC_VMPY2H UNSPEC_ARC_VMPY2HU UNSPEC_ARC_STKTIE - ]) -(define_c_enum "vunspec" [ VUNSPEC_ARC_RTIE VUNSPEC_ARC_SYNC VUNSPEC_ARC_BRK @@ -5802,21 +5800,19 @@ }) (define_insn "fls" - [(set (match_operand:SI 0 "dest_reg_operand" "=w,w") - (unspec:SI [(match_operand:SI 1 "general_operand" "cL,Cal")] + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:SI 1 "nonmemory_operand" "rL,Cal")] UNSPEC_ARC_FLS))] "TARGET_NORM && TARGET_V2" - "@ - fls \t%0, %1 - fls \t%0, %1" + "fls\\t%0,%1" [(set_attr "length" "4,8") (set_attr "type" "two_cycle_core,two_cycle_core")]) (define_insn "seti" - [(unspec_volatile:SI [(match_operand:SI 0 "general_operand" "rL")] + [(unspec_volatile:SI [(match_operand:SI 0 "nonmemory_operand" "rL")] VUNSPEC_ARC_SETI)] "TARGET_V2" - "seti %0" + "seti\\t%0" [(set_attr "length" "4") (set_attr "type" "misc")]) |