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| author | Doug Evans <dje@gnu.org> | 1996-03-05 07:16:53 +0000 |
|---|---|---|
| committer | Doug Evans <dje@gnu.org> | 1996-03-05 07:16:53 +0000 |
| commit | 9ad2334b60dab68c60b33bb2c87b9590c6a4002a (patch) | |
| tree | 93a7432b6adc943a70e6e312281a9c12c34bfc75 /gcc | |
| parent | 7ea7263d65d04281dde9edbe5d1c9cc4edb0918e (diff) | |
| download | gcc-9ad2334b60dab68c60b33bb2c87b9590c6a4002a.zip gcc-9ad2334b60dab68c60b33bb2c87b9590c6a4002a.tar.gz gcc-9ad2334b60dab68c60b33bb2c87b9590c6a4002a.tar.bz2 | |
sparc.md (*cmp{si,di}_insn): %r0 -> %0.
* sparc/sparc.md (*cmp{si,di}_insn): %r0 -> %0.
(DFmode move split): Ensure registers not extended v9 fp regs.
(*mov{sf,df,tf}_cc_reg_sp64): %r3 -> %3.
From-SVN: r11437
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/sparc/sparc.md | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index 95ee2b0..0cd7ddb 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -348,7 +348,7 @@ (compare:CC (match_operand:SI 0 "register_operand" "r") (match_operand:SI 1 "arith_operand" "rI")))] "" - "cmp %r0,%1" + "cmp %0,%1" [(set_attr "type" "compare")]) (define_insn "*cmpsf_fpe_sp32" @@ -404,7 +404,7 @@ (compare:CCX (match_operand:DI 0 "register_operand" "r") (match_operand:DI 1 "arith_double_operand" "rHI")))] "TARGET_ARCH64" - "cmp %r0,%1" + "cmp %0,%1" [(set_attr "type" "compare")]) (define_insn "*cmpsf_fpe_sp64" @@ -2183,11 +2183,13 @@ ;; Must handle overlapping registers here, since parameters can be unaligned ;; in registers. -;; ??? Do we need a v9 version of this? + (define_split [(set (match_operand:DF 0 "register_operand" "") (match_operand:DF 1 "register_operand" ""))] - "! TARGET_ARCH64 && reload_completed" + "! TARGET_ARCH64 && reload_completed + && REGNO (operands[0]) < SPARC_FIRST_V9_FP_REG + && REGNO (operands[1]) < SPARC_FIRST_V9_FP_REG" [(set (match_dup 2) (match_dup 3)) (set (match_dup 4) (match_dup 5))] " @@ -2575,7 +2577,7 @@ (match_operand:SF 3 "register_operand" "f") (match_operand:SF 4 "register_operand" "0")))] "TARGET_ARCH64 && TARGET_FPU" - "fmovrs%D1 %2,%r3,%0" + "fmovrs%D1 %2,%3,%0" [(set_attr "type" "cmove")]) (define_insn "*movdf_cc_reg_sp64" @@ -2586,7 +2588,7 @@ (match_operand:DF 3 "register_operand" "e") (match_operand:DF 4 "register_operand" "0")))] "TARGET_ARCH64 && TARGET_FPU" - "fmovrd%D1 %2,%r3,%0" + "fmovrd%D1 %2,%3,%0" [(set_attr "type" "cmove")]) (define_insn "*movtf_cc_reg_sp64" @@ -2597,7 +2599,7 @@ (match_operand:TF 3 "register_operand" "e") (match_operand:TF 4 "register_operand" "0")))] "TARGET_ARCH64 && TARGET_FPU" - "fmovrq%D1 %2,%r3,%0" + "fmovrq%D1 %2,%3,%0" [(set_attr "type" "cmove")]) (define_insn "*movsf_ccfp_sp64" |