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| author | Shiva Chen <shiva0217@gmail.com> | 2015-06-09 08:15:23 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <ktkachov@gcc.gnu.org> | 2015-06-09 08:15:23 +0000 |
| commit | 99e9cec839abe5e78575545ae648f02508307c9a (patch) | |
| tree | 4baff2f0e514fad3304e217366d87a372fae178b /gcc | |
| parent | d9c16ed274d6390a46a7d2e4466315d9c70f23fb (diff) | |
| download | gcc-99e9cec839abe5e78575545ae648f02508307c9a.zip gcc-99e9cec839abe5e78575545ae648f02508307c9a.tar.gz gcc-99e9cec839abe5e78575545ae648f02508307c9a.tar.bz2 | |
[GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code
On behalf of Shiva Chen
2015-06-09 Shiva Chen <shiva0217@gmail.com>
* sync.md (atomic_load<mode>): Add conditional code for lda/ldr
(atomic_store<mode>): Likewise.
2015-06-09 Shiva Chen <shiva0217@gmail.com>
* gcc.target/arm/stl-cond.c: New test.
From-SVN: r224269
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/arm/sync.md | 14 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/stl-cond.c | 19 |
4 files changed, 36 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4af3495..95a6df4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2015-06-09 Shiva Chen <shiva0217@gmail.com> + + * sync.md (atomic_load<mode>): Add conditional code for lda/ldr + (atomic_store<mode>): Likewise. + 2015-06-09 Richard Biener <rguenther@suse.de> * cfgloop.c (get_loop_body_in_bfs_order): Fix assert. diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index 44cda61..75dd52e 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -75,11 +75,12 @@ { enum memmodel model = memmodel_from_int (INTVAL (operands[2])); if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_release (model)) - return \"ldr<sync_sfx>\\t%0, %1\"; + return \"ldr%(<sync_sfx>%)\\t%0, %1\"; else - return \"lda<sync_sfx>\\t%0, %1\"; + return \"lda<sync_sfx>%?\\t%0, %1\"; } -) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) (define_insn "atomic_store<mode>" [(set (match_operand:QHSI 0 "memory_operand" "=Q") @@ -91,11 +92,12 @@ { enum memmodel model = memmodel_from_int (INTVAL (operands[2])); if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_acquire (model)) - return \"str<sync_sfx>\t%1, %0\"; + return \"str%(<sync_sfx>%)\t%1, %0\"; else - return \"stl<sync_sfx>\t%1, %0\"; + return \"stl<sync_sfx>%?\t%1, %0\"; } -) + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no")]) ;; Note that ldrd and vldr are *not* guaranteed to be single-copy atomic, ;; even for a 64-bit aligned address. Instead we use a ldrexd unparied diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5c21d29..a51682a 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2015-06-09 Shiva Chen <shiva0217@gmail.com> + + * gcc.target/arm/stl-cond.c: New test. + 2015-06-09 Richard Biener <rguenther@suse.de> PR middle-end/66413 diff --git a/gcc/testsuite/gcc.target/arm/stl-cond.c b/gcc/testsuite/gcc.target/arm/stl-cond.c new file mode 100644 index 0000000..de14bb5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/stl-cond.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arm_ok } */ +/* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-options "-O2 -marm" } */ +/* { dg-add-options arm_arch_v8a } */ + +struct backtrace_state +{ + int threaded; + int lock_alloc; +}; + +void foo (struct backtrace_state *state) +{ + if (state->threaded) + __sync_lock_release (&state->lock_alloc); +} + +/* { dg-final { scan-assembler "stlne" } } */ |