[testsuite] Enable pr94600-{1,3}.c tests for nvptx

When compiling test-case pr94600-1.c for nvptx, this gimple mem move:
...
  MEM[(volatile struct t0 *)655404B] ={v} a0[0];
...
is expanded into a memcpy, but when compiling pr94600-2.c instead, this similar
gimple mem move:
...
  MEM[(volatile struct t0 *)655404B] ={v} a00;
...
is expanded into a 32-bit load/store pair.

In both cases, emit_block_move is called.

In the latter case, can_move_by_pieces (4 /* byte-size */, 32 /* bit-align */)
is called, which returns true (because by_pieces_ninsns returns 1, which is
smaller than the MOVE_RATIO of 4).

In the former case, can_move_by_pieces (4 /* byte-size */, 8 /* bit-align */)
is called, which returns false (because by_pieces_ninsns returns 4, which is
not smaller than the MOVE_RATIO of 4).

So the difference in code generation is explained by the alignment.  The
difference in alignment comes from the move sources: a0[0] vs. a00.  Both
have the same type with 8-bit alignment, but a00 is on stack, which based on
the base stack align and stack variable placement happens to result in a
32-bit alignment.

Enable test-cases pr94600-{1,3}.c for nvptx by forcing the currently 8-byte
aligned variables to have a 32-bit alignment for STRICT_ALIGNMENT targets.

Tested on nvptx.

gcc/testsuite/ChangeLog:

2020-10-01  Tom de Vries  <tdevries@suse.de>

	* gcc.dg/pr94600-1.c: Force 32-bit alignment for a0 for !non_strict_align
	targets.  Remove target clauses from scan tests.
	* gcc.dg/pr94600-3.c: Same.

2 files changed, 16 insertions, 6 deletions

diff --git a/gcc/testsuite/gcc.dg/pr94600-1.c b/gcc/testsuite/gcc.dg/pr94600-1.c
index c9a7bb9..149e4f3 100644
--- a/gcc/testsuite/gcc.dg/pr94600-1.c
+++ b/gcc/testsuite/gcc.dg/pr94600-1.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target size32plus } */
 /* { dg-options "-fdump-rtl-final -O2" } */
+/* { dg-additional-options "-DALIGN_VAR" { target { ! non_strict_align } } } */
 
 /* Assignments to a whole struct of suitable size (32 bytes) must not be
    picked apart into field accesses. */
@@ -12,7 +13,11 @@ typedef struct {
   unsigned int f3 : 7;
 } t0;
 
-static t0 a0[] = {
+static t0 a0[]
+#ifdef ALIGN_VAR
+__attribute__((aligned (4)))
+#endif
+  = {
  { .f0 = 7, .f1 = 99, .f3 = 1, },
  { .f0 = 7, .f1 = 251, .f3 = 1, },
  { .f0 = 8, .f1 = 127, .f3 = 5, },
@@ -32,5 +37,5 @@ foo(void)
 }
 
 /* The only volatile accesses should be the obvious writes.  */
-/* { dg-final { scan-rtl-dump-times {\(mem/v} 6 "final" { target { non_strict_align || pcc_bitfield_type_matters } } } } */
-/* { dg-final { scan-rtl-dump-times {\(set \(mem/v} 6 "final" { target { non_strict_align || pcc_bitfield_type_matters } } } } */
+/* { dg-final { scan-rtl-dump-times {\(mem/v} 6 "final" } } */
+/* { dg-final { scan-rtl-dump-times {\(set \(mem/v} 6 "final" } } */
diff --git a/gcc/testsuite/gcc.dg/pr94600-3.c b/gcc/testsuite/gcc.dg/pr94600-3.c
index ff42c7d..2fce9f1 100644
--- a/gcc/testsuite/gcc.dg/pr94600-3.c
+++ b/gcc/testsuite/gcc.dg/pr94600-3.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target size32plus } */
 /* { dg-options "-fdump-rtl-final -O2 -fno-unroll-loops" } */
+/* { dg-additional-options "-DALIGN_VAR" { target { ! non_strict_align } } } */
 
 /* Same-address version of pr94600-1.c. */
 
@@ -11,7 +12,11 @@ typedef struct {
   unsigned int f3 : 7;
 } t0;
 
-static t0 a0[] = {
+static t0 a0[]
+#ifdef ALIGN_VAR
+__attribute__((aligned (4)))
+#endif
+  = {
  { .f0 = 7, .f1 = 99, .f3 = 1, },
  { .f0 = 7, .f1 = 251, .f3 = 1, },
  { .f0 = 8, .f1 = 127, .f3 = 5, },
@@ -31,5 +36,5 @@ foo(void)
 }
 
 /* The loop isn't unrolled. */
-/* { dg-final { scan-rtl-dump-times {\(mem/v} 1 "final" { target { non_strict_align || pcc_bitfield_type_matters } } } } */
-/* { dg-final { scan-rtl-dump-times {\(set \(mem/v} 1 "final" { target { non_strict_align || pcc_bitfield_type_matters } } } } */
+/* { dg-final { scan-rtl-dump-times {\(mem/v} 1 "final" } } */
+/* { dg-final { scan-rtl-dump-times {\(set \(mem/v} 1 "final" } } */