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| author | Richard Sandiford <richard.sandiford@arm.com> | 2019-08-07 18:47:26 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2019-08-07 18:47:26 +0000 |
| commit | 8ad84de26e1032d80225905c611a47b64a385e8a (patch) | |
| tree | 3c69ff330423305e70aaca431303877676232851 /gcc | |
| parent | cb18e86dd005fe009c536a8bb0aec7aa88ca66df (diff) | |
| download | gcc-8ad84de26e1032d80225905c611a47b64a385e8a.zip gcc-8ad84de26e1032d80225905c611a47b64a385e8a.tar.gz gcc-8ad84de26e1032d80225905c611a47b64a385e8a.tar.bz2 | |
[AArch64] Remove redundant SVE FADDA pattern
*pred_fold_left_plus_<mode> could no longer match anything, since
UNSPEC_FADDA now takes three operands. Predicated FADDAs should
now go through mask_fold_left_plus_<mode> instead.
2019-08-07 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-sve.md (*pred_fold_left_plus_<mode>): Delete.
From-SVN: r274186
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-sve.md | 15 |
2 files changed, 4 insertions, 15 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index aa0ad4a..c292eec 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2019-08-07 Richard Sandiford <richard.sandiford@arm.com> + * config/aarch64/aarch64-sve.md (*pred_fold_left_plus_<mode>): Delete. + +2019-08-07 Richard Sandiford <richard.sandiford@arm.com> + * config/aarch64/iterators.md (UNSPEC_COND_ADD): Rename to... (UNSPEC_COND_FADD): ...this. (UNSPEC_COND_SUB): Rename to... diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index b66066b..6c40979 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -3468,21 +3468,6 @@ "fadda\t%<Vetype>0, %3, %<Vetype>0, %2.<Vetype>" ) -;; Predicated form of the above in-order reduction. -(define_insn "*pred_fold_left_plus_<mode>" - [(set (match_operand:<VEL> 0 "register_operand" "=w") - (unspec:<VEL> - [(match_operand:<VEL> 1 "register_operand" "0") - (unspec:SVE_F - [(match_operand:<VPRED> 2 "register_operand" "Upl") - (match_operand:SVE_F 3 "register_operand" "w") - (match_operand:SVE_F 4 "aarch64_simd_imm_zero")] - UNSPEC_SEL)] - UNSPEC_FADDA))] - "TARGET_SVE" - "fadda\t%<Vetype>0, %2, %<Vetype>0, %3.<Vetype>" -) - ;; ========================================================================= ;; == Permutes ;; ========================================================================= |