diff options
| author | Will Schmidt <will_schmidt@vnet.ibm.com> | 2020-09-17 17:17:15 -0500 |
|---|---|---|
| committer | Will Schmidt <will_schmidt@vnet.ibm.com> | 2020-10-22 09:42:52 -0500 |
| commit | 8732511910e1dd23c56c01e876bbe235c360ac55 (patch) | |
| tree | b56f03f767618c10be8237c9dbe95d37ae42a250 /gcc | |
| parent | dfb7345cd54e90b4f5cc0234bd37ec2763602180 (diff) | |
| download | gcc-8732511910e1dd23c56c01e876bbe235c360ac55.zip gcc-8732511910e1dd23c56c01e876bbe235c360ac55.tar.gz gcc-8732511910e1dd23c56c01e876bbe235c360ac55.tar.bz2 | |
[PATCH, rs6000] int128 sign extention instructions (partial prereq)
Hi
This is a sub-set of the 128-bit sign extension support patch series
that will be fully implemented in a subsequent patch from Carl.
This is a necessary pre-requisite for the vector-load/store rightmost
element patch that follows in this thread.
[v2] Refreshed and touched up per review comments.
- updated set_attr entries. removed superfluous set_attr entries.
- moved define_insn and define_expand entries to vsx.md.
gcc/ChangeLog:
* config/rs6000/vsx.md (enum unspec): Add
UNSPEC_EXTENDDITI2 and UNSPEC_MTVSRD_DITI_W1 entries.
(mtvsrdd_diti_w1, extendditi2_vector): New define_insns.
(extendditi2): New define_expand.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/rs6000/vsx.md | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index d962693..398efa3 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -352,6 +352,8 @@ UNSPEC_VSX_FIRST_MISMATCH_EOS_INDEX UNSPEC_XXGENPCV UNSPEC_MTVSBM + UNSPEC_EXTENDDITI2 + UNSPEC_MTVSRD_DITI_W1 UNSPEC_VCNTMB UNSPEC_VEXPAND UNSPEC_VEXTRACT @@ -4795,6 +4797,37 @@ "vextsw2d %0,%1" [(set_attr "type" "vecexts")]) +;; ISA 3.1 vector sign extend +;; Move DI value from GPR to TI mode in VSX register, word 1. +(define_insn "mtvsrdd_diti_w1" + [(set (match_operand:TI 0 "register_operand" "=wa") + (unspec:TI [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_MTVSRD_DITI_W1))] + "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" + "mtvsrdd %x0,0,%1" + [(set_attr "type" "vecmove")]) + +;; Sign extend 64-bit value in TI reg, word 1, to 128-bit value in TI reg +(define_insn "extendditi2_vector" + [(set (match_operand:TI 0 "gpc_reg_operand" "=v") + (unspec:TI [(match_operand:TI 1 "gpc_reg_operand" "v")] + UNSPEC_EXTENDDITI2))] + "TARGET_POWER10" + "vextsd2q %0,%1" + [(set_attr "type" "vecexts")]) + +(define_expand "extendditi2" + [(set (match_operand:TI 0 "gpc_reg_operand") + (sign_extend:DI (match_operand:DI 1 "gpc_reg_operand")))] + "TARGET_POWER10" + { + /* Move 64-bit src from GPR to vector reg and sign extend to 128-bits. */ + rtx temp = gen_reg_rtx (TImode); + emit_insn (gen_mtvsrdd_diti_w1 (temp, operands[1])); + emit_insn (gen_extendditi2_vector (operands[0], temp)); + DONE; + }) + ;; ISA 3.0 Binary Floating-Point Support |