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authorMaciej W. Rozycki <macro@embecosm.com>2022-01-28 11:55:12 +0000
committerMaciej W. Rozycki <macro@embecosm.com>2022-01-28 11:55:12 +0000
commit833e651a76cbab26d18307fe761b609c0fa61439 (patch)
treef7e025728e0f96ae5655bba2e19d6497a79a832b /gcc
parent26e237fb5b83582b30ef7c5a388bc4e968a5a289 (diff)
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RISC-V: Document `auipc' and `bitmanip' `type' attributes
Document new `auipc' and `bitmanip' `type' attributes added respectively with commit 88108b27dda9 ("RISC-V: Add sifive-7 pipeline description.") and commit 283b1707f237 ("RISC-V: Implement instruction patterns for ZBA extension.") but not listed so far. gcc/ * config/riscv/riscv.md: Document `auipc' and `bitmanip' `type' attributes.
Diffstat (limited to 'gcc')
-rw-r--r--gcc/config/riscv/riscv.md2
1 files changed, 2 insertions, 0 deletions
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 0492392..b3c5bce 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -150,6 +150,7 @@
;; mfc transfer from coprocessor
;; const load constant
;; arith integer arithmetic instructions
+;; auipc integer addition to PC
;; logical integer logical instructions
;; shift integer shift instructions
;; slt set less than instructions
@@ -167,6 +168,7 @@
;; multi multiword sequence (or user asm statements)
;; nop no operation
;; ghost an instruction that produces no real code
+;; bitmanip bit manipulation instructions
(define_attr "type"
"unknown,branch,jump,call,load,fpload,store,fpstore,
mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,