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| author | Jakub Jelinek <jakub@redhat.com> | 2020-03-13 11:33:16 +0100 |
|---|---|---|
| committer | Jakub Jelinek <jakub@redhat.com> | 2020-03-13 11:33:16 +0100 |
| commit | 7aa605c9d4643dc6e0a0460e5697c02457cd7278 (patch) | |
| tree | 16882cf3765fa4a87b7ac652fb84afd03e80c67a /gcc | |
| parent | fd8679974b2ded884ffd7d912efef7fe13e4ff4f (diff) | |
| download | gcc-7aa605c9d4643dc6e0a0460e5697c02457cd7278.zip gcc-7aa605c9d4643dc6e0a0460e5697c02457cd7278.tar.gz gcc-7aa605c9d4643dc6e0a0460e5697c02457cd7278.tar.bz2 | |
aarch64: Fix another bug in aarch64_add_offset_1 [PR94121]
> I'm getting this ICE with -mabi=ilp32:
>
> during RTL pass: fwprop1
> /opt/gcc/gcc-20200312/gcc/testsuite/gcc.dg/pr94121.c: In function 'bar':
> /opt/gcc/gcc-20200312/gcc/testsuite/gcc.dg/pr94121.c:16:1: internal compiler error: in decompose, at rtl.h:2279
That is a preexisting issue, caused by another bug in the same function.
When mode is SImode and moffset is 0x80000000 (or anything else with the
bit 31 set), we need to sign-extend it.
2020-03-13 Jakub Jelinek <jakub@redhat.com>
PR target/94121
* config/aarch64/aarch64.c (aarch64_add_offset_1): Use gen_int_mode
instead of GEN_INT.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 3 |
2 files changed, 8 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 25abfcf..448c1e1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2020-03-13 Jakub Jelinek <jakub@redhat.com> + + PR target/94121 + * config/aarch64/aarch64.c (aarch64_add_offset_1): Use gen_int_mode + instead of GEN_INT. + 2020-03-13 H.J. Lu <hongjiu.lu@intel.com> PR target/89229 diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 2c81f86..b0cbb6e2 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -3757,7 +3757,8 @@ aarch64_add_offset_1 (scalar_int_mode mode, rtx dest, if (emit_move_imm) { gcc_assert (temp1 != NULL_RTX || can_create_pseudo_p ()); - temp1 = aarch64_force_temporary (mode, temp1, GEN_INT (moffset)); + temp1 = aarch64_force_temporary (mode, temp1, + gen_int_mode (moffset, mode)); } insn = emit_insn (offset < 0 ? gen_sub3_insn (dest, src, temp1) |