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| author | Chung-Ju Wu <jasonwucj@gmail.com> | 2018-04-05 02:05:06 +0000 |
|---|---|---|
| committer | Chung-Ju Wu <jasonwucj@gcc.gnu.org> | 2018-04-05 02:05:06 +0000 |
| commit | 77827557f67584ca88ba16a93b224447ea234965 (patch) | |
| tree | a86dc9cd17623b9b275eb5f92a9702dd2b85961f /gcc | |
| parent | 9c1a4c0fa1ea371bd23b2867836d97f3de45bbbd (diff) | |
| download | gcc-77827557f67584ca88ba16a93b224447ea234965.zip gcc-77827557f67584ca88ba16a93b224447ea234965.tar.gz gcc-77827557f67584ca88ba16a93b224447ea234965.tar.bz2 | |
[NDS32] Fine-tune predicator for alu-shift patterns.
gcc/
* config/nds32/nds32.md (*sub_srli, *and_slli): Fine-tune predicator.
From-SVN: r259115
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/nds32/nds32.md | 24 |
2 files changed, 16 insertions, 12 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 74c3e02..fe76138 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2018-04-05 Chung-Ju Wu <jasonwucj@gmail.com> + * config/nds32/nds32.md (*sub_srli, *and_slli): Fine-tune predicator. + +2018-04-05 Chung-Ju Wu <jasonwucj@gmail.com> + * config/nds32/nds32.md: Adjust indention. 2018-04-05 Kito Cheng <kito.cheng@gmail.com> diff --git a/gcc/config/nds32/nds32.md b/gcc/config/nds32/nds32.md index d8aecad..0189bdf 100644 --- a/gcc/config/nds32/nds32.md +++ b/gcc/config/nds32/nds32.md @@ -434,10 +434,10 @@ (set_attr "length" "4")]) (define_insn "*sub_srli" - [(set (match_operand:SI 0 "register_operand" "= r") - (minus:SI (match_operand:SI 1 "register_operand" " r") - (lshiftrt:SI (match_operand:SI 2 "register_operand" " r") - (match_operand:SI 3 "immediate_operand" " Iu05"))))] + [(set (match_operand:SI 0 "register_operand" "= r") + (minus:SI (match_operand:SI 1 "register_operand" " r") + (lshiftrt:SI (match_operand:SI 2 "register_operand" " r") + (match_operand:SI 3 "nds32_imm5u_operand" " Iu05"))))] "TARGET_ISA_V3" "sub_srli\t%0, %1, %2, %3" [(set_attr "type" "alu_shift") @@ -626,20 +626,20 @@ (set_attr "feature" "v3m, v1, v1, v1, v1, v1,v3m,v3m, v1, v1, v1, v3,pe1")]) (define_insn "*and_slli" - [(set (match_operand:SI 0 "register_operand" "= r") - (and:SI (ashift:SI (match_operand:SI 1 "register_operand" " r") - (match_operand:SI 2 "immediate_operand" " Iu05")) - (match_operand:SI 3 "register_operand" " r")))] + [(set (match_operand:SI 0 "register_operand" "= r") + (and:SI (ashift:SI (match_operand:SI 1 "register_operand" " r") + (match_operand:SI 2 "nds32_imm5u_operand" " Iu05")) + (match_operand:SI 3 "register_operand" " r")))] "TARGET_ISA_V3" "and_slli\t%0, %3, %1, %2" [(set_attr "type" "alu_shift") (set_attr "length" "4")]) (define_insn "*and_srli" - [(set (match_operand:SI 0 "register_operand" "= r") - (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" " r") - (match_operand:SI 2 "immediate_operand" " Iu05")) - (match_operand:SI 3 "register_operand" " r")))] + [(set (match_operand:SI 0 "register_operand" "= r") + (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" " r") + (match_operand:SI 2 "nds32_imm5u_operand" " Iu05")) + (match_operand:SI 3 "register_operand" " r")))] "TARGET_ISA_V3" "and_srli\t%0, %3, %1, %2" [(set_attr "type" "alu_shift") |