diff options
| author | Richard Kenner <kenner@gcc.gnu.org> | 1995-09-28 14:24:12 -0400 |
|---|---|---|
| committer | Richard Kenner <kenner@gcc.gnu.org> | 1995-09-28 14:24:12 -0400 |
| commit | 75fbfd0c125bbde33fd02d07b03f85f944ec9ba2 (patch) | |
| tree | 01c80a0ea719d432eaab02513be036d8c14522be /gcc | |
| parent | 63d77adf435de2c2f21672da6c39927653bf8333 (diff) | |
| download | gcc-75fbfd0c125bbde33fd02d07b03f85f944ec9ba2.zip gcc-75fbfd0c125bbde33fd02d07b03f85f944ec9ba2.tar.gz gcc-75fbfd0c125bbde33fd02d07b03f85f944ec9ba2.tar.bz2 | |
(anonymous DImode shift patterns setting cc0): Turned off due to
reload problems.
From-SVN: r10411
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/m68k/m68k.md | 59 |
1 files changed, 30 insertions, 29 deletions
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md index 4c54862..8068356 100644 --- a/gcc/config/m68k/m68k.md +++ b/gcc/config/m68k/m68k.md @@ -4384,35 +4384,36 @@ ;; logical shift instructions -(define_insn "" - [(set (cc0) - (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro") - (const_int 32)) 1)) - (set (match_operand:SI 1 "general_operand" "=dm") - (subreg:SI (lshiftrt:DI (match_operand:DI 2 "general_operand" "0") - (const_int 32)) 1))] - "" - "* -{ - return \"move%.l %0,%1\"; -} ") - -(define_insn "" - [(set (cc0) - (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro") - (const_int 32)) 0)) - (set (match_operand:DI 1 "general_operand" "=do") - (lshiftrt:DI (match_operand:DI 2 "general_operand" "0") - (const_int 32)))] - "" - "* -{ - if (GET_CODE (operands[1]) == REG) - operands[2] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); - else - operands[2] = adj_offsettable_operand (operands[1], 4); - return \"move%.l %0,%2\;clr%.l %1\"; -} ") +;; commented out because of reload problems in 950612-1.c +;;(define_insn "" +;; [(set (cc0) +;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro") +;; (const_int 32)) 1)) +;; (set (match_operand:SI 1 "general_operand" "=dm") +;; (subreg:SI (lshiftrt:DI (match_dup 0) +;; (const_int 32)) 1))] +;; "" +;; "* +;;{ +;; return \"move%.l %0,%1\"; +;;} ") +;; +;;(define_insn "" +;; [(set (cc0) +;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro") +;; (const_int 32)) 0)) +;; (set (match_operand:DI 1 "general_operand" "=do") +;; (lshiftrt:DI (match_dup 0) +;; (const_int 32)))] +;; "" +;; "* +;;{ +;; if (GET_CODE (operands[1]) == REG) +;; operands[2] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); +;; else +;; operands[2] = adj_offsettable_operand (operands[1], 4); +;; return \"move%.l %0,%2\;clr%.l %1\"; +;;} ") (define_insn "subreg1lshrdi_const32" [(set (match_operand:SI 0 "general_operand" "=rm") |