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| author | Richard Stallman <rms@gnu.org> | 1992-10-31 05:46:36 +0000 |
|---|---|---|
| committer | Richard Stallman <rms@gnu.org> | 1992-10-31 05:46:36 +0000 |
| commit | 71cd5224b3f1f86a9b5f5701dd5e1e92e8535fd0 (patch) | |
| tree | 3f66806150bd1228e10f5d717e97bb430fcc4ae6 /gcc | |
| parent | baa599cab6b539734c80c721ea194e45772bf728 (diff) | |
| download | gcc-71cd5224b3f1f86a9b5f5701dd5e1e92e8535fd0.zip gcc-71cd5224b3f1f86a9b5f5701dd5e1e92e8535fd0.tar.gz gcc-71cd5224b3f1f86a9b5f5701dd5e1e92e8535fd0.tar.bz2 | |
(addsi3, subsi3): Don't allow -32768 as the second operand;
the assembler complains if the instruction fills a delay slot.
From-SVN: r2661
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/mips/mips.md | 32 |
1 files changed, 27 insertions, 5 deletions
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 8f3274b..d5a9faa 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -293,16 +293,27 @@ (set_attr "mode" "SF") (set_attr "length" "1")]) -(define_insn "addsi3" +(define_expand "addsi3" [(set (match_operand:SI 0 "register_operand" "=d") - (plus:SI (match_operand:SI 1 "arith_operand" "%d") + (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ") (match_operand:SI 2 "arith_operand" "dI")))] "" + " +{ + if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == -32768) + operands[2] = force_reg (SImode, operands[2]); +}") + +(define_insn "addsi3_internal" + [(set (match_operand:SI 0 "register_operand" "=d") + (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ") + (match_operand:SI 2 "arith_operand" "dI")))] + "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768" "* { return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) - ? \"subu\\t%0,%1,%n2\" - : \"addu\\t%0,%1,%2\"; + ? \"subu\\t%0,%z1,%n2\" + : \"addu\\t%0,%z1,%2\"; }" [(set_attr "type" "arith") (set_attr "mode" "SI") @@ -485,11 +496,22 @@ (set_attr "mode" "SF") (set_attr "length" "1")]) -(define_insn "subsi3" +(define_expand "subsi3" [(set (match_operand:SI 0 "register_operand" "=d") (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ") (match_operand:SI 2 "arith_operand" "dI")))] "" + " +{ + if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == -32768) + operands[2] = force_reg (SImode, operands[2]); +}") + +(define_insn "subsi3_internal" + [(set (match_operand:SI 0 "register_operand" "=d") + (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ") + (match_operand:SI 2 "arith_operand" "dI")))] + "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768" "* { return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) |