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| author | Alan Modra <amodra@gmail.com> | 2012-08-01 07:44:44 +0930 |
|---|---|---|
| committer | Alan Modra <amodra@gcc.gnu.org> | 2012-08-01 07:44:44 +0930 |
| commit | 7099ce06b06e1899b2c4a8aac93829a34b0b7108 (patch) | |
| tree | 780cb30ed2133a9b4ca64aed7bd56e5bf9e83e5f /gcc | |
| parent | fdc43210e38125c34a8578e1fb8f7b09c396c14c (diff) | |
| download | gcc-7099ce06b06e1899b2c4a8aac93829a34b0b7108.zip gcc-7099ce06b06e1899b2c4a8aac93829a34b0b7108.tar.gz gcc-7099ce06b06e1899b2c4a8aac93829a34b0b7108.tar.bz2 | |
re PR target/54131 (ICE building 416.gamess, reload_cse_simplify_operands)
PR target/54131
* config/rs6000/rs6000.c (mem_operand_gpr): Don't limit range
of lo_sum offsets. Comment. Assert mode at least word size
rather than bypassing powerpc64 word offset check.
From-SVN: r190022
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 26 |
2 files changed, 27 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a137c7f..1947fdf 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2012-08-01 Alan Modra <amodra@gmail.com> + + PR target/54131 + * config/rs6000/rs6000.c (mem_operand_gpr): Don't limit range + of lo_sum offsets. Comment. Assert mode at least word size + rather than bypassing powerpc64 word offset check. + 2012-07-31 Bill Schmidt <wschmidt@linux.ibm.com> * config/rs6000/rs6000.c (rs6000_builtin_vectorization_cost): Revise diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index b68082c..34948fb 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -5070,24 +5070,38 @@ address_offset (rtx op) Offsetting a lo_sum should not be allowed, except where we know by alignment that a 32k boundary is not crossed, but see the ??? - comment in rs6000_legitimize_reload_address. */ + comment in rs6000_legitimize_reload_address. Note that by + "offsetting" here we mean a further offset to access parts of the + MEM. It's fine to have a lo_sum where the inner address is offset + from a sym, since the same sym+offset will appear in the high part + of the address calculation. */ bool mem_operand_gpr (rtx op, enum machine_mode mode) { unsigned HOST_WIDE_INT offset; int extra; + rtx addr = XEXP (op, 0); - op = address_offset (XEXP (op, 0)); + op = address_offset (addr); if (op == NULL_RTX) return true; offset = INTVAL (op); - extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD; - if (extra < 0) - extra = 0; - else if (TARGET_POWERPC64 && (offset & 3) != 0) + if (TARGET_POWERPC64 && (offset & 3) != 0) return false; + + if (GET_CODE (addr) == LO_SUM) + /* We know by alignment that ABI_AIX medium/large model toc refs + will not cross a 32k boundary, since all entries in the + constant pool are naturally aligned and we check alignment for + other medium model toc-relative addresses. For ABI_V4 and + ABI_DARWIN lo_sum addresses, we just check that 64-bit + offsets are 4-byte aligned. */ + return true; + + extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD; + gcc_assert (extra >= 0); return offset + 0x8000 < 0x10000u - extra; } |