diff options
| author | Maciej W. Rozycki <macro@linux-mips.org> | 2020-10-12 19:09:13 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@linux-mips.org> | 2020-10-12 19:09:13 +0100 |
| commit | 6f0a4ae1274cc41ee9d9a142af5e51e416a2c08d (patch) | |
| tree | bc504e40cef98e66afb9b17c945f4a47ba06acc5 /gcc | |
| parent | 46f4a397ab0907ce5786e1f0b92030a73e8b89ef (diff) | |
| download | gcc-6f0a4ae1274cc41ee9d9a142af5e51e416a2c08d.zip gcc-6f0a4ae1274cc41ee9d9a142af5e51e416a2c08d.tar.gz gcc-6f0a4ae1274cc41ee9d9a142af5e51e416a2c08d.tar.bz2 | |
MIPS/libphobos: Fix switchcontext.S assembly for MIPS I ISA
Correct MIPS I assembly build errors in switchcontext.S:
.../libphobos/libdruntime/config/mips/switchcontext.S: Assembler messages:
.../libphobos/libdruntime/config/mips/switchcontext.S:50: Error: opcode not supported on this processor: mips1 (mips1) `sdc1 $f20,(0*8-((6*8+4+(-6*8+4&7))))($sp)'
etc., due to the use of the MIPS II LDC1 and SDC1 hardware instructions
for FP register load and store operations. Instead use the L.D and S.D
generic assembly instructions, which are strict aliases for the LDC1 and
SDC1 instructions respectively and produce identical machine code where
the assembly for the MIPS II or a higher ISA has been requested, however
they become assembly macros and expand to compatible sequences of LWC1
and SWC1 hardware instructions where the assembly for the MIPS I ISA is
in effect.
libphobos/
* libdruntime/config/mips/switchcontext.S [__mips_hard_float]:
Use L.D and S.D generic assembly instructions rather than LDC1
and SDC1 MIPS II hardware instructions.
Diffstat (limited to 'gcc')
0 files changed, 0 insertions, 0 deletions