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| author | Daniel Jacobowitz <dan@codesourcery.com> | 2009-04-14 20:19:54 +0000 |
|---|---|---|
| committer | Nathan Froyd <froydnj@gcc.gnu.org> | 2009-04-14 20:19:54 +0000 |
| commit | 6cd1d2e205a1067b67da328e89ebfc83f90ad625 (patch) | |
| tree | 64b5b4b2b60cecaa2f1aaf3a3a5daa89d40db6e6 /gcc | |
| parent | 68a607d8143693c8f4bc66bef001197ea4ff7c84 (diff) | |
| download | gcc-6cd1d2e205a1067b67da328e89ebfc83f90ad625.zip gcc-6cd1d2e205a1067b67da328e89ebfc83f90ad625.tar.gz gcc-6cd1d2e205a1067b67da328e89ebfc83f90ad625.tar.bz2 | |
rs6000.c (rs6000_dwarf_register_span): Fix debug output for other floating point modes.
* config/rs6000/rs6000.c (rs6000_dwarf_register_span): Fix debug
output for other floating point modes.
From-SVN: r146060
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 36 |
2 files changed, 29 insertions, 12 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index eae5095..cbdc1a4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2009-04-14 Daniel Jacobowitz <dan@codesourcery.com> + + * config/rs6000/rs6000.c (rs6000_dwarf_register_span): Fix debug + output for other floating point modes. + 2009-04-14 Diego Novillo <dnovillo@google.com> Le-Chun Wu <lcwu@google.com> diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 2352989..9035d13 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -22689,12 +22689,16 @@ rs6000_is_opaque_type (const_tree type) static rtx rs6000_dwarf_register_span (rtx reg) { - unsigned regno; + rtx parts[8]; + int i, words; + unsigned regno = REGNO (reg); + enum machine_mode mode = GET_MODE (reg); if (TARGET_SPE + && regno < 32 && (SPE_VECTOR_MODE (GET_MODE (reg)) - || (TARGET_E500_DOUBLE - && (GET_MODE (reg) == DFmode || GET_MODE (reg) == DDmode)))) + || (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) + && mode != SFmode && mode != SDmode && mode != SCmode))) ; else return NULL_RTX; @@ -22704,15 +22708,23 @@ rs6000_dwarf_register_span (rtx reg) /* The duality of the SPE register size wreaks all kinds of havoc. This is a way of distinguishing r0 in 32-bits from r0 in 64-bits. */ - return - gen_rtx_PARALLEL (VOIDmode, - BYTES_BIG_ENDIAN - ? gen_rtvec (2, - gen_rtx_REG (SImode, regno + 1200), - gen_rtx_REG (SImode, regno)) - : gen_rtvec (2, - gen_rtx_REG (SImode, regno), - gen_rtx_REG (SImode, regno + 1200))); + words = (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD; + gcc_assert (words <= 4); + for (i = 0; i < words; i++, regno++) + { + if (BYTES_BIG_ENDIAN) + { + parts[2 * i] = gen_rtx_REG (SImode, regno + 1200); + parts[2 * i + 1] = gen_rtx_REG (SImode, regno); + } + else + { + parts[2 * i] = gen_rtx_REG (SImode, regno); + parts[2 * i + 1] = gen_rtx_REG (SImode, regno + 1200); + } + } + + return gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (words * 2, parts)); } /* Fill in sizes for SPE register high parts in table used by unwinder. */ |