Merge branch 'master' into devel/sphinx

9 files changed, 78 insertions, 7 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c1fc2ec..a687dc5 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,22 @@
+2022-10-16  Jeff Law  <jeffreyalaw@gmail.com>
+
+	* config/h8300/constraints.md (Z0..Z7): New register
+	constraints.
+	* config/h8300/h8300.h (reg_class): Add new classes.
+	(REG_CLASS_NAMES): Similarly.
+	(REG_CLASS_CONTENTS): Similarly.
+
+2022-10-16  Jeff Law  <jeffreyalaw@gmail.com>
+
+	* config/h8300/constraints.md (Zz constraint): Renamed
+	from "z".
+	* config/h8300/movepush.md (movqi_h8sx, movhi_h8sx): Adjust
+	constraint to use Zz instead of Z.
+
+2022-10-16  Jeff Law  <jeffreyalaw@gmail.com>
+
+	* config/h8300/h8300.cc (h8300_register_move_cost): Fix typo.
+
 2022-10-14  Aldy Hernandez  <aldyh@redhat.com>
 
 	* value-range.cc (frange::set): Implement distinction between
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 88e8f3f..856b00b 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20221015
+20221017
diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
index bbced8a..b5c1b21 100644
--- a/gcc/common/config/i386/cpuinfo.h
+++ b/gcc/common/config/i386/cpuinfo.h
@@ -496,6 +496,12 @@ get_intel_cpu (struct __processor_model *cpu_model,
     case 0x9a:
     case 0xbf:
       /* Alder Lake.  */
+    case 0xb7:
+      /* Raptor Lake.  */
+    case 0xb5:
+    case 0xaa:
+    case 0xac:
+      /* Meteor Lake.  */
       cpu = "alderlake";
       CHECK___builtin_cpu_is ("corei7");
       CHECK___builtin_cpu_is ("alderlake");
diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc
index c0c2ad7..d6a68dc 100644
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -1929,6 +1929,10 @@ const pta processor_alias_table[] =
     M_CPU_SUBTYPE (INTEL_COREI7_SAPPHIRERAPIDS), P_PROC_AVX512F},
   {"alderlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
     M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
+  {"raptorlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
+    M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
+  {"meteorlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
+    M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
   {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
     M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
   {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 8d5972f..2af30b4 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -1082,6 +1082,11 @@ case ${target} in
   # Assume that newlib is being used and so __cxa_atexit is provided.
   default_use_cxa_atexit=yes
   use_gcc_stdint=wrap
+
+  case "${with_newlib}-${with_headers}" in
+  no-no) use_gcc_stdint=provide ;;
+  *) ;;
+  esac
   ;;
 esac
 
diff --git a/gcc/config/h8300/constraints.md b/gcc/config/h8300/constraints.md
index 2836232..6eaffc1 100644
--- a/gcc/config/h8300/constraints.md
+++ b/gcc/config/h8300/constraints.md
@@ -211,8 +211,33 @@
   (and (match_code "const_int")
        (match_test "exact_log2 (ival & 0xff) != -1")))
 
-(define_constraint "Z"
+(define_constraint "Zz"
   "@internal"
   (and (match_test "TARGET_H8300SX")
        (match_code "mem")
        (match_test "CONSTANT_P (XEXP (op, 0))")))
+
+(define_register_constraint "Z0" "NOT_R0_REGS"
+  "@internal")
+
+(define_register_constraint "Z1" "NOT_R1_REGS"
+  "@internal")
+
+(define_register_constraint "Z2" "NOT_R2_REGS"
+  "@internal")
+
+(define_register_constraint "Z3" "NOT_R3_REGS"
+  "@internal")
+
+(define_register_constraint "Z4" "NOT_R4_REGS"
+  "@internal")
+
+(define_register_constraint "Z5" "NOT_R5_REGS"
+  "@internal")
+
+(define_register_constraint "Z6" "NOT_R6_REGS"
+  "@internal")
+
+(define_register_constraint "Z7" "NOT_SP_REGS"
+  "@internal")
+
diff --git a/gcc/config/h8300/h8300.cc b/gcc/config/h8300/h8300.cc
index 78cf15f..be3e385 100644
--- a/gcc/config/h8300/h8300.cc
+++ b/gcc/config/h8300/h8300.cc
@@ -1140,7 +1140,7 @@ static int
 h8300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
                          reg_class_t from, reg_class_t to)
 {
-  if (from == MAC_REGS || to == MAC_REG)
+  if (from == MAC_REGS || to == MAC_REGS)
     return 6;
   else
     return 3;
diff --git a/gcc/config/h8300/h8300.h b/gcc/config/h8300/h8300.h
index 9a6c78c..45cc4fc 100644
--- a/gcc/config/h8300/h8300.h
+++ b/gcc/config/h8300/h8300.h
@@ -282,6 +282,8 @@ extern const char * const *h8_reg_names;
 
 enum reg_class {
   NO_REGS, COUNTER_REGS, SOURCE_REGS, DESTINATION_REGS,
+  NOT_R0_REGS, NOT_R1_REGS, NOT_R2_REGS, NOT_R3_REGS,
+  NOT_R4_REGS, NOT_R5_REGS, NOT_R6_REGS, NOT_SP_REGS,
   GENERAL_REGS, MAC_REGS, ALL_REGS, LIM_REG_CLASSES
 };
 
@@ -291,6 +293,8 @@ enum reg_class {
 
 #define REG_CLASS_NAMES \
 { "NO_REGS", "COUNTER_REGS", "SOURCE_REGS", "DESTINATION_REGS", \
+  "NOT_R0_REGS", "NOT_R1_REGS", "NOT_R2_REGS", "NOT_R3_REGS", \
+  "NOT_R4_REGS", "NOT_R5_REGS", "NOT_R6_REGS", "NOT_SP_REGS", \
   "GENERAL_REGS", "MAC_REGS", "ALL_REGS", "LIM_REGS" }
 
 /* Define which registers fit in which classes.
@@ -302,6 +306,14 @@ enum reg_class {
    {0x010},		/* COUNTER_REGS */	\
    {0x020},		/* SOURCE_REGS */	\
    {0x040},		/* DESTINATION_REGS */	\
+   {0x0fe},		/* NOT_R0_REGS */	\
+   {0x0fd},		/* NOT_R1_REGS */	\
+   {0x0fb},		/* NOT_R2_REGS */	\
+   {0x0f7},		/* NOT_R3_REGS */	\
+   {0x0ef},		/* NOT_R4_REGS */	\
+   {0x0df},		/* NOT_R5_REGS */	\
+   {0x0bf},		/* NOT_R6_REGS */	\
+   {0x07f},		/* NOT_SP_REGS */	\
    {0xeff},		/* GENERAL_REGS */	\
    {0x100},		/* MAC_REGS */		\
    {0xfff},		/* ALL_REGS	*/	\
diff --git a/gcc/config/h8300/movepush.md b/gcc/config/h8300/movepush.md
index ada4ddd..e895de8 100644
--- a/gcc/config/h8300/movepush.md
+++ b/gcc/config/h8300/movepush.md
@@ -28,7 +28,7 @@
   [(set (attr "length") (symbol_ref "compute_mov_length (operands)"))])
 
 (define_insn_and_split "*movqi_h8sx"
-  [(set (match_operand:QI 0 "general_operand_dst" "=Z,rQ")
+  [(set (match_operand:QI 0 "general_operand_dst" "=Zz,rQ")
 	(match_operand:QI 1 "general_operand_src" "P4>X,rQi"))]
   "TARGET_H8300SX"
   "#"
@@ -37,7 +37,7 @@
 	      (clobber (reg:CC CC_REG))])])
 
 (define_insn "*movqi_h8sx<cczn>"
-  [(set (match_operand:QI 0 "general_operand_dst" "=Z,rQ")
+  [(set (match_operand:QI 0 "general_operand_dst" "=Zz,rQ")
 	(match_operand:QI 1 "general_operand_src" "P4>X,rQi"))
    (clobber (reg:CC CC_REG))]
   "TARGET_H8300SX"
@@ -113,7 +113,7 @@
   [(set (attr "length") (symbol_ref "compute_mov_length (operands)"))])
 
 (define_insn_and_split "*movhi_h8sx"
-  [(set (match_operand:HI 0 "general_operand_dst" "=r,r,Z,Q,rQ")
+  [(set (match_operand:HI 0 "general_operand_dst" "=r,r,Zz,Q,rQ")
 	(match_operand:HI 1 "general_operand_src" "I,P3>X,P4>X,IP8>X,rQi"))]
   "TARGET_H8300SX"
   "#"
@@ -122,7 +122,7 @@
 	      (clobber (reg:CC CC_REG))])])
   
 (define_insn "*movhi_h8sx<cczn>"
-  [(set (match_operand:HI 0 "general_operand_dst" "=r,r,Z,Q,rQ")
+  [(set (match_operand:HI 0 "general_operand_dst" "=r,r,Zz,Q,rQ")
 	(match_operand:HI 1 "general_operand_src" "I,P3>X,P4>X,IP8>X,rQi"))
    (clobber (reg:CC CC_REG))]
   "TARGET_H8300SX"